Datasheet

AD5501 Data Sheet
Rev. C | Page 4 of 20
SPECIFICATIONS
V
DD
= 10 V to 62 V; V
LOGIC
= 2.3 V to 5.5 V; R
L
= 60 kΩ; C
L
= 200 pF; −40°C < T
A
< +105°C, unless otherwise noted.
Table 2.
Parameter Symbol Min Typ
1
Max Unit Test Conditions/Comments
ACCURACY
2
Resolution 12 Bits
Differential Nonlinearity DNL −1 +1 LSB
Integral Nonlinearity INL
60 V Mode −1 +1 LSB V
= 62 V
30 V Mode −2 +2 LSB V
= 62 V
V
OUT
Temperature Coefficient
3, 4
50
ppm/°C
Offset Error V
OE
65 +100 mV
Offset Error Drift
4
60 µV/°C
Zero-Scale Error V
ZSE
80 mV
Zero-Scale Error Drift
4
50 µV/°C 60 V mode
Full-Scale Error V
FSE
−325 +275 mV
Full-Scale Error Drift
4
1 mV/°C −40°C to +25°C; 60 V mode
350 µV/°C +25°C to +105°C; 60 V mode
Gain Error −0.6 +0.6 % of FSR
Gain Temperature Coefficient
4
10 ppm of FSR/°C
OUTPUT CHARACTERISTICS
Output Voltage Range
5
AGND + 0.5 V
DD
0.5 V
Short-Circuit Current
4, 6
2 mA
Capacitive Load Stability
4
1 V to 4 V step
R
L
= 60 kΩ to 1 nF
Load Current
4
−1 +1 mA
Feedback Resistance
7
100
DC Output Impedance
4
3
DC Output Leakage
4
10 µA
DIGITAL INPUTS
Input Logic High V
IH
2.0 V V
= 4.5 V to 5.5 V
1.8 V V
= 2.3 V to 3.6 V
Input Logic Low V
IL
0.8 V V
= 2.3 V to 5.5 V
Input Current I
IL
±1 µA
Input Capacitance
4
I
IC
5 pF
DIGITAL OUTPUTS
Output High Voltage V
OH
V
LOGIC
0.4 V V I
= 200 µA
Output Low Voltage V
OL
DGND + 0.4 V V I
= 200 µA
Three-State Leakage Current
SDI, SDO, SCLK,
LDAC
,
CLR
,
R_SEL
Pins
−1 +1 µA
ALARM
Pin −10 +10 µA
Output Capacitance
4
5 pF