Datasheet

ManualsBrandsANALOG DEVICES ManualsData collecting ICsData acquisition IC - DA converter (DAC) CSPBGA 74

32-Channel, 14-Bit

Voltage-Output DAC

AD5532

Rev. D

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FEATURES

High integration:

32-channel DAC in 12 mm × 12 mm CSPBGA

Adjustable voltage output range

Guaranteed monotonic

Readback capability

DSP/microcontroller compatible serial interface

Output impedance:

0.5 Ω (AD5532-1, AD5532-2)

500 Ω (AD5532-3)

1 kΩ (AD5532-5)

Output voltage span:

10 V (AD5532-1, AD5532-3, AD5532-5)

20 V (AD5532-2)

Infinite sample-and-hold capability to ±0.018% accuracy

Temperature range −40°C to +85°C

APPLICATIONS

Automatic test equipment

Optical networks

Level setting

Instrumentation

Industrial control systems

Data acquisition

Low cost I/O

GENERAL DESCRIPTION

The AD5532

is a 32-channel, 14-bit voltage-output DAC with

an additional infinite sample-and-hold mode. The selected

DAC register is written to via the 3-wire serial interface; V

OUT

for this DAC is then updated to reflect the new contents of the

DAC register. DAC selection is accomplished via Address Bits

A0–A4. The output voltage range is determined by the offset

voltage at the OFFS_IN pin and the gain of the output amplifier.

It is restricted to a range from V

+ 2 V to V

– 2 V because of

the headroom of the output amplifier.

The device is operated with AV

= 5 V ± 5%; DV

= 2.7 V to

5.25 V; V

= −4.75 V to −16.5 V; and V

= 8 V to 16.5 V. The

AD5532 requires a stable 3 V reference on REF_IN as well as an

offset voltage on OFFS_IN.

PRODUCT HIGHLIGHTS

1. 32-channel, 14-bit DAC in one package, guaranteed

monotonic.

2. Available in a 74-lead CSPBGA package with a body size of

12 mm ×12 mm.

3. Droopless/infinite sample-and-hold mode.

00939-C-001

SCLK D

OUT

A4–A0 CAL OFFSET_SEL

AD5532

ADDRESS INPUT REGISTER

DAC

ADC

MUX DAC

MODE

14-BIT BUS

TRACK/RESET

BUSY

DAC_GND

AGND

DGND

INTERFACE

CONTROL

LOGIC

SER/PAR

OUT

OFFS_OUT

OUT

REF_IN REF_OUT OFFS_IN V

SYNC/CS

Figure 1. Functional Block Diagram

Summary of content (20 pages)

PAGE 1
32-Channel, 14-Bit Voltage-Output DAC AD5532 FEATURES GENERAL DESCRIPTION High integration: 32-channel DAC in 12 mm × 12 mm CSPBGA Adjustable voltage output range Guaranteed monotonic Readback capability DSP/microcontroller compatible serial interface Output impedance: 0.5 Ω (AD5532-1, AD5532-2) 500 Ω (AD5532-3) 1 kΩ (AD5532-5) Output voltage span: 10 V (AD5532-1, AD5532-3, AD5532-5) 20 V (AD5532-2) Infinite sample-and-hold capability to ±0.
PAGE 2
AD5532 TABLE OF CONTENTS Specifications..................................................................................... 3 Output Buffer Stage—Gain and Offset.................................... 14 ISHA Mode.................................................................................... 5 Offset Voltage Channel .............................................................. 14 Timing Characteristics..................................................................... 6 Reset Function ...........
PAGE 3
AD5532 SPECIFICATIONS VDD = 8 V to 16.5 V, VSS = –4.75 V to –16.5 V; AVCC = 4.75 V to 5.25 V; DVCC = 2.7 V to 5.25 V; AGND = DGND = DAC_GND = 0 V; REF_IN = 3 V; output range from VSS + 2 V to VDD − 2 V. All outputs unloaded. All specifications TMIN to TMAX, unless otherwise noted. Table 1.
PAGE 4
AD5532 A Version 1 AD5532-1/-3/-5 AD5532-2 Only 10 10 Unit pF max Conditions/Comments 0.4 4.0 0.4 2.4 ±1 15 0.4 4.0 0.4 2.4 ±1 15 V max V min V max V min μA max pF typ Sinking 200 μA. Sourcing 200 μA. Sinking 200 μA. Sourcing 200 μA. DOUT only. DOUT only. 8/16.5 −4.75/−16.5 4.75/5.25 2.7/5.25 8/16.5 −4.75/−16.5 4.75/5.25 2.7/5.25 V min/max V min/max V min/max V min/max 15 15 mA max 15 15 mA max 33 1.5 280 33 1.
PAGE 5
AD5532 ISHA MODE Table 2. 2 Parameter ANALOG CHANNEL VIN to VOUT Nonlinearity 3 Offset Error Gain ANALOG INPUT (VIN) Input Voltage Range Input Lower Dead Band Input Upper Dead Band Input Current Input Capacitance 4 ANALOG INPUT (OFFS_IN) Input Current Input Voltage Range AC CHARACTERISTICS Output Settling Time4 Acquisition Time AC Crosstalk4 A Version 1 AD5532-1/-3/-5 AD5532-2 Only Unit Conditions/Comments ±0.018 ±50 3.46/3.52/3.6 ±0.018 ±75 6.96/7/7.02 % max mV max min/typ/max ±0.
PAGE 6
AD5532 TIMING CHARACTERISTICS PARALLEL INTERFACE Table 3. Parameter 1, 2 t1 t2 t3 t4 t5 t6 1 2 Limit at TMIN, TMAX (A Version) 0 0 50 50 20 7 Unit ns min ns min ns min ns min ns min ns min Conditions/Comments CS to WR setup time CS to WR hold time CS pulse width low WR pulse width low A4–A0, CAL, OFFS_SEL to WR setup time A4–A0, CAL, OFFS_SEL to WR hold time See Figure 2 and Figure 3, the parallel interface timing diagrams. Guaranteed by design and characterization, not production tested.
PAGE 7
AD5532 SERIAL INTERFACE Table 4.
PAGE 8
AD5532 ABSOLUTE MAXIMUM RATINGS TA = 25°C unless otherwise noted. Table 5.
PAGE 9
AD5532 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 2 3 4 5 6 7 8 9 10 11 A A B B C C D D E E F F TOP VIEW G H H J J K K L L 1 2 3 4 5 6 7 8 9 10 11 00939-C-028 G Figure 7. 74-Lead CSPBGA Ball Configuration Table 6.
PAGE 10
AD5532 Table 7. Pin Function Descriptions Pin AGND (1–2) AVCC (1–2) VDD (1–4) VSS (1–4) DGND DVCC DAC_GND (1–2) REF_IN REF_OUT VOUT (0–31) VIN A4–A1, A0 CAL CS/SYNC WR OFFSET_SEL SCLK DIN DOUT SER/PAR OFFS_IN OFFS_OUT BUSY TRACK/RESET Function Analog GND pins. Analog Supply pins. Voltage range from 4.75 V to 5.25 V. VDD Supply pins. Voltage range from 8 V to 16.5 V. VSS Supply pins. Voltage range from –4.75 V to –16.5 V. Digital GND pins. Digital Supply pins. Voltage range from 2.7 V to 5.25 V.
PAGE 11
AD5532 TERMINOLOGY Output Noise Spectral Density DAC MODE This is a measure of the maximum deviation from a straight line passing through the endpoints of the DAC transfer function. It is expressed as a percentage of full-scale span. This is a measure of internally generated random noise. Random noise is characterized as a spectral density (voltage per root Hertz). It is measured by loading all DACs to midscale and measuring noise at the output. It is measured in nV/(√Hz).
PAGE 12
AD5532 TYPICAL PERFORMANCE CHARACTERISTICS 1.0 3.535 VREFIN = 3V 0.8 VOFFS_IN = 0V TA = 25°C 0.6 TA = 25°C VREFIN = 3V 3.530 0.2 VOUT (V) DNL ERROR (LSB) 0.4 0 –0.2 3.525 –0.4 –0.8 –1.0 0 2k 4k 6k 8k 10k DAC CODE 12k 14k 00939-C-012 00939-C-009 –0.6 3.520 16k 6 10 0.2 1.0 8 DNL MAX 0 0 INL MIN DNL MIN TA = 25°C VREFIN = 3V VOFFS_IN = 0.5V 4 2 –0.1 –0.2 0 40 TEMPERATURE (°C) 00939-C-013 00939-C-010 0 –1.0 –40 –6 6 VOUT (V) INL ERROR (% FSR) DNL ERROR (LSB) –4 0.
PAGE 13
AD5532 0.024 70k TA = 25°C 0.020 VREFIN = 3V V = 0V 0.016 OFFS_IN 63791 60k 50k 0.008 FREQUENCY 0.004 0 –0.004 40k 30k –0.008 20k –0.012 00939-C-015 –0.016 –0.020 –0.024 0.10 2.96 VIN (V) Figure 16. VIN to VOUT Accuracy after Offset and Gain Adjustment (ISHA Mode) 5V 100 BUSY 90 VOUT TA = 25°C VREFIN = 3V VIN = 0 → 1.5V 10 1V 2μs 00939-C-016 0% Figure 17. Acquisition Time and Output Settling Time (ISHA Mode) Rev. D | Page 13 of 20 10k 1545 200 0 5.2670 5.2676 VOUT (V) 5.
PAGE 14
AD5532 FUNCTIONAL DESCRIPTION The AD5532 consists of 32 DACs and an ADC (for ISHA mode) in a single package. In DAC mode, a 14-bit digital word is loaded into one of the 32 DAC Registers via the serial interface. This is then converted (with gain and offset) into an analog output voltage (VOUT0–VOUT31). To update a DAC’s output voltage, the required DAC is addressed via the serial port. When the DAC address and code have been loaded, the selected DAC converts the code.
PAGE 15
AD5532 1. ISHA Mode TRACK FUNCTION (ISHA MODE) Typically in ISHA mode of operation TRACK is held high and the channel begins to acquire when it is addressed. However, if TRACK is low when the channel is addressed, VIN is switched to the output buffer and an acquisition on the channel does not occur until a rising edge of TRACK.
PAGE 16
AD5532 not shift data in or out until it receives the falling edge of the SYNC signal. SERIAL INTERFACE The serial interface allows easy interfacing to most microcontrollers and DSPs, such as the PIC16C, PIC17C, QSPI, SPI, DSP56000, TMS320, and ADSP-21xx, without the need for any glue logic. When interfacing to the 8051, the SCLK must be inverted. The Microprocessor Interfacing section explains how to interface to some popular DSPs and microcontrollers.
PAGE 17
AD5532 PARALLEL INTERFACE (ISHA MODE ONLY) Figure 22 shows the connection diagram. AD5532* Table 11. WR A4–A0 OFFSET_SEL CAL Description Active low package select pin. This pin is shared with the SYNC function for the serial interface. Active low write pin. The values on the address pins are latched on a rising edge of WR. Five address pins (A4 = MSB of address, A0 = LSB). These are used to address the relevant channel (out of a possible 32). Offset select pin.
PAGE 18
AD5532 AD5532 to PIC16C6x/7x The PIC16C6x/7x synchronous serial port (SSP) is configured as an SPI master with the Clock Polarity Bit = 0. This is done by writing to the synchronous serial port control register (SSPCON). See the PIC16/17 Microcontroller User Manual. In this example, the I/O port RA1 is being used to pulse SYNC and enable the serial port of the AD5532.
PAGE 19
AD5532 Typical Application Circuit (ISHA Mode) The AD5532 can be used to set up voltage levels on 32 channels as shown in the circuit that follows. An AD780 provides the 3 V reference for the AD5532 and for the AD5541 16-bit DAC. A simple 3-wire interface is used to write to the AD5541. Because the AD5541 has an output resistance of 6.25 kΩ(typ), the time taken to charge/discharge the capacitance at the VIN pin is significant. Hence an AD820 is used to buffer the DAC output.
PAGE 20
AD5532 OUTLINE DIMENSIONS A1 CORNER INDEX AREA 12.00 BSC SQ 11 10 9 8 7 6 5 4 3 2 1 BALL A1 INDICATOR 10.00 BSC SQ BOTTOM VIEW TOP VIEW 1.00 BSC A B C D E F G H J K L DETAIL A 1.70 MAX DETAIL A 1.10 0.25 0.30 MIN 0.20 COPLANARITY SEATING PLANE 061306-A 0.70 0.60 0.50 BALL DIAMETER COMPLIANT TO JEDEC STANDARDS MO-192-ABD-1 Figure 29.