Datasheet

ManualsBrandsANALOG DEVICES ManualsData collecting ICsData acquisition IC - DA converter (DAC) SOIC 14 N

2.7 V to 5.5 V, Serial-Input,

Voltage-Output, 14-Bit DACs

AD5551/AD5552

Rev. A

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FEATURES

Full 14-bit performance

3 V and 5 V single supply operation

Low 0.625 mW power dissipation

1 μs settling time

Unbuffered voltage output capable of driving 60 kΩ

loads directly

SPI/QSPI/MICROWIRE-compatible interface standards

Power-on reset clears DAC output to 0 V (unipolar mode)

5 kV HBM ESD classification

APPLICATIONS

Digital gain and offset adjustment

Automatic test equipment

Data acquisition systems

Industrial process control

GENERAL DESCRIPTION

The AD5551/AD5552 are single, 14-bit, serial-input, voltage-

output DACs that operate from a single 2.7 V to 5.5 V supply.

The DAC output range extends from 0 V to V

REF

These DACs provide 14-bit performance without any adjust-

ments. The DAC output is unbuffered, which reduces power

consumption and offset errors contributed by an output buffer.

With an external op amp, the AD5552 can be operated in

bipolar mode generating a ±V

REF

output swing. The AD5552

also includes Kelvin sense connections for the reference and

analog ground pins to reduce layout sensitivity. For higher

precision applications, refer to 16-bit DACs AD5541, AD5542,

and AD5544.

The AD5551/AD5552 utilize a versatile 3-wire interface that is

compatible with SPI, QSPI™, MICROWIRE™, and DSP interface

standards. The AD5551 and AD5552 are available in 8-lead and

14-lead SOIC packages.

FUNCTIONAL BLOCK DIAGRAMS

14-BIT DAC

14-BIT DATA LATCH

SERIAL INPUT REGISITER

DGND

DIN

REF

CLK

OUT

AGND

AD5551

CONTROL

LOGIC

01943-001

Figure 1.

14-BIT DATA LATCH

SERIAL INPUT REGISITER

DGND

LDAC

SCLK

DIN

REFS

REFF

OUT

RFB

INV

AD5552

AGNDF

AGNDS

14-BIT DAC

INV

CONTROL

LOGIC

01943-002

Figure 2.

PRODUCT HIGHLIGHTS

1. Single Supply Operation.

The AD5551 and AD5552 are fully specified and

guaranteed for a single 2.7 V to 5.5 V supply.

2. Low Power Consumption.

Typically 0.625 mW with a 5 V supply.

3. 3-Wire Serial Interface.

4. Unbuffered output capable of driving 60 k loads, which

reduces power consumption as there is no internal buffer

to drive.

5. Power-On Reset Circuitry.

Summary of content (16 pages)

PAGE 1
2.7 V to 5.5 V, Serial-Input, Voltage-Output, 14-Bit DACs AD5551/AD5552 FEATURES FUNCTIONAL BLOCK DIAGRAMS VDD Full 14-bit performance 3 V and 5 V single supply operation Low 0.
PAGE 2
AD5551/AD5552 TABLE OF CONTENTS Features .............................................................................................. 1 Bipolar Output Operation ......................................................... 12 Applications ....................................................................................... 1 Output Amplifier Selection....................................................... 12 General Description .........................................................................
PAGE 3
AD5551/AD5552 SPECIFICATIONS VDD = 2.7 V to 5.5 V, 2.5 V ≤ VREF ≤ VDD, AGND = DGND = 0 V. All specifications TA = TMIN to TMAX, unless otherwise noted. Table 1.
PAGE 4
AD5551/AD5552 TIMING CHARACTERISTICS VDD = 2.7 V to 5.5 V, 2.5 V ≤ VREF ≤ 5.5 V, AGND = DGND = 0 V. All specifications −40°C ≤ TA ≤ +85°C, unless otherwise noted. Table 2.
PAGE 5
AD5551/AD5552 ABSOLUTE MAXIMUM RATINGS TA = 25°C unless otherwise noted Table 3. Parameter VDD to AGND Digital Input Voltage to DGND VOUT to AGND AGND, AGNDF, AGNDS to DGND Input Current to Any Pin Except Supplies Operating Temperature Range Industrial (B Version) Storage Temperature Range Maximum Junction Temperature, (TJ max) Package Power Dissipation Thermal Impedance SOIC (R-8) SOIC (R-14) Lead Temperature, Soldering Peak Temperature1 ESD2 1 2 Rating –0.3 V to +6 V –0.3 V to VDD + 0.3 V –0.
PAGE 6
AD5551/AD5552 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS RFB 1 14 VDD VOUT 2 13 INV 12 DGND AGNDF 3 AD5552 VREF 3 CS 4 8 AD5551 VDD 7 DGND TOP VIEW (Not to Scale) 6 DIN 5 SCLK CS 7 01943-004 VOUT 1 AGND 2 11 LDAC TOP VIEW (Not to Scale) 10 DIN VREFS 5 9 NC VREFF 6 8 SCLK NC = NO CONNECNT 01943-005 AGNDS 4 Figure 5. AD5552 Pin Configuration Figure 4. AD5551 Pin Configuration Table 4. AD5551 Pin Function Descriptions Pin No.
PAGE 7
AD5551/AD5552 TYPICAL PERFORMANCE CHARACTERISTICS 0.125 0.125 0 –0.062 –0.125 0 8192 16,384 24,576 32,768 40,960 49,152 57,344 65,536 CODE 0.062 0 –0.062 –0.125 0 8192 Figure 6. Integral Nonlinearity vs. Code Figure 9. Differential Nonlinearity vs. Code 0.062 0.187 DIFFERENTIAL NONLINEARITY (LSB) 0 –0.062 –0.125 –0.187 –0.250 –60 –40 –20 0 20 40 60 80 TEMPERATURE (°C) 100 120 140 VDD = 5V VREF = 2.5V 0.125 0.062 0 –0.062 –0.125 –60 01943-007 Figure 7.
PAGE 8
AD5551/AD5552 0 0.037 VDD = 5V VREF = 2.5V TA = 25°C –0.025 0.025 ZERO-CODE ERROR (LSB) GAIN ERROR (LSB) –0.050 –0.075 –0.100 –0.125 –0.150 –0.175 VDD = 5V VREF = 2.5V TA = 25°C 0.012 0 –0.012 –0.025 –40 25 TEMPERATURE (°C) –0.037 01943-012 –0.225 85 Figure 12. Gain Error vs. Temperature 25 TEMPERATURE (°C) 85 Figure 15. Zero-Code Offset Error vs. Temperature 132 2.0 VDD = 5V VREF = 2.5V 130 TA = 25°C TA = 25°C 128 SUPPLY CURRENT (µA) SUPPLY CURRENT (µA) –40 01943-015 –0.
PAGE 9
AD5551/AD5552 VREF = 2.5V VDD = 5V TA = 25°C VREF = 2.5V VDD = 5V TA = 25°C 2µs/DIV CS (5V/DIV) DIN (5V/DIV) 10pF 50pF 100pF 200pF VOUT (0.5V/DIV) 01943-018 2µs/DIV Figure 18. Digital Feedthrough Figure 20. Large Signal Settling Time 5 1.236 CS –10 1.230 –15 1.228 VOUT –20 1.226 VOUT (50mV/DIV) GAIN = –216 –25 0 0.5 1.0 1.5 TIME (ns) 01943-019 0.5µs/DIV –30 2.0 Figure 19. Digital-to-Analog Glitch Impulse Figure 21. Small Signal Settling Time Rev. A | Page 9 of 16 01943-021 1.
PAGE 10
AD5551/AD5552 TERMINOLOGY Relative Accuracy For the DAC, relative accuracy or integral nonlinearity (INL) is a measure of the maximum deviation, in LSBs, from a straight line passing through the endpoints of the DAC transfer function. A typical INL vs. code plot can be seen in Figure 6. Differential Nonlinearity Differential nonlinearity is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes.
PAGE 11
AD5551/AD5552 THEORY OF OPERATION The AD5551/AD5552 are single, 14-bit, serial input, voltage output DACs. They operate from a single supply ranging from 2.7 V to 5.5 V and consume typically 125 μA with a supply of 5 V. Data is written to these devices in a 14-bit word format, via a 3-or 4-wire serial interface. To ensure a known power-up state, these parts were designed with a power-on reset function. In unipolar mode, the output is reset to 0 V, while in bipolar mode, the AD5552 output is set to −VREF.
PAGE 12
AD5551/AD5552 Assuming a perfect reference, the worst-case output voltage may be calculated from the following equation: VOUT −UNI = Assuming a perfect reference, the worst-case bipolar output voltage may be calculated from the following equation. D × (VREF + VGE ) + VZSE + INL 214 VOUT − BIP = where: VOUT–UNI is the unipolar mode worst-case output. D is the decimal code loaded to the DAC. VREF is the reference voltage applied to part. VGE is the gain error in volts.
PAGE 13
AD5551/AD5552 REFERENCE AND GROUND POWER-ON RESET As the input impedance is code-dependent, the reference pin should be driven from a low-impedance source. The AD5551/ AD5552 operate with a voltage reference ranging from 2 V to VDD. Although DAC’s full-scale output voltage is determined by the reference, references below 2 V results in reduced accuracy. Table 6 and Table 7 outline the analog output voltage for particular digital codes.
PAGE 14
AD5551/AD5552 MICROPROCESSOR INTERFACING MICROWIRE TO AD5551/AD5552 INTERFACE Figure 27 shows an interface between the AD5551/AD5552 and any MICROWIRE-compatible device. Serial data is shifted out on the falling edge of the serial clock and into the AD5551/ AD5552 on the rising edge of the serial clock. No glue logic is required as the DAC clocks data into the input shift register on the rising edge. CS SO DIN SCLK SCLK *ADDITIONAL PINS OMITTED FOR CLARITY. Figure 27.
PAGE 15
AD5551/AD5552 APPLICATIONS INFORMATION OPTOCOUPLER INTERFACE DECODING MULTIPLE AD5551/AD5552S The digital inputs of the AD5551/AD5552 are Schmitttriggered, so they can accept slow transitions on the digital input lines. This makes these parts ideal for industrial applications where it may be necessary that the DAC is isolated from the controller via optocouplers. Figure 29 illustrates such an interface. The CS pin of the AD5551/AD5552 can be used to select one of a number of DACs.
PAGE 16
AD5551/AD5552 OUTLINE DIMENSIONS 5.00 (0.1968) 4.80 (0.1890) 5 1 4 1.27 (0.0500) BSC 0.25 (0.0098) 0.10 (0.0040) 6.20 (0.2441) 5.80 (0.2284) 1.75 (0.0688) 1.35 (0.0532) 0.51 (0.0201) 0.31 (0.0122) COPLANARITY 0.10 SEATING PLANE 0.50 (0.0196) 0.25 (0.0099) 45° 8° 0° 0.25 (0.0098) 0.17 (0.0067) 1.27 (0.0500) 0.40 (0.