Datasheet

ManualsBrandsANALOG DEVICES ManualsData collecting ICsData acquisition IC - DA converter (DAC) TSSOP 14

Quad, 12-/14-/16-Bit nanoDACs with

5 ppm/°C On-Chip Reference, I

C Interface

Data Sheet

AD5625R/AD5645R/AD5665R, AD5625/AD5665

Rev. C Document Feedback

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FEATURES

Low power, smallest pin-compatible, quad nanoDACs

AD5625R/AD5645R/AD5665R

12-/14-/16-bit nanoDACs

On-chip, 2.5 V, 5 ppm/°C reference in TSSOP

On-chip, 2.5 V, 10 ppm/°C reference in LFCSP

On-chip, 1.25 V, 10 ppm/°C reference in LFCSP

AD5625/AD5665

12-/16-bit nanoDACs

External reference only

3 mm × 3 mm, 10-lead LFCSP; 14-lead TSSOP; and 1.665 mm

× 2.245 mm, 12-ball WLCSP

2.7 V to 5.5 V power supply

Guaranteed monotonic by design

Power-on reset to zero scale/midscale

Per channel power-down

Hardware

LDAC

and

CLR

functions

C-compatible serial interface supports standard (100 kHz),

fast (400 kHz), and high speed (3.4 MHz) modes

APPLICATIONS

Process control

Data acquisition systems

Portable battery-powered instruments

Digital gain and offset adjustment

Programmable voltage and current sources

Programmable attenuators

GENERAL DESCRIPTION

The AD5625R/AD5645R/AD5665R and AD5625/AD5665

members of the nanoDAC® family are low power, quad, 12-/

14-/16-bit, buffered voltage-out DACs with/without an on-chip

reference. All devices operate from a single 2.7 V to 5.5 V supply,

are guaranteed monotonic by design, and have an I

C-compatible

serial interface.

The AD5625R/AD5645R/AD5665R have an on-chip reference. The

LFCSP versions of the AD56x5R have a 1.25 V or 2.5 V, 10 ppm/°C

reference, giving a full-scale output range of 2.5 V or 5 V; the

TSSOP versions of the AD56x5R have a 2.5 V, 5 ppm/°C refer-

ence, giving a full-scale output range of 5 V. The WLCSP package

has a 1.25 V reference. The on-chip reference is off at power-up,

allowing the use of an external reference. The internal reference is

enabled via a software write. The AD5625/AD5665 require an

external reference voltage to set the output range of the DAC.

The part incorporates a power-on reset circuit that ensures that

the DAC output powers up to 0 V (POR = GND) or midscale

(POR = V

) and remains there until a valid write occurs. The

on-chip precision output amplifier enables rail-to-rail output swing.

FUNCTIONAL BLOCK DIAGRAMS

Figure 1. AD5625R/AD5645R/AD5665R

Figure 2. AD5625/AD5665

The AD56x5R/AD56x5 use a 2-wire I

C-compatible serial

interface that operates in standard (100 kHz), fast (400 kHz),

and high speed (3.4 MHz) modes.

Table 1. Related Devices

Part No. Description

AD5025/AD5045/AD5065 Dual 12-/14-/16-bit DACs

AD5624R/AD5644R/AD5664R,

AD5624/AD5664

Quad SPI 12-/14-/16-bit DACs,

with/without internal reference

AD5627R/AD5647R/AD5667R,

AD5627/AD5667

Dual I

C 12-/14-/16-bit DACs,

with/without internal reference

AD5666 Quad SPI 16-bit DAC with internal

reference

INTERFACE

LOGIC

SDA

SCL

DDR1

DDR2

GND

1.25V/2.5V REF

REFIN

REFOUT

AD5625R/AD5645R/AD5665R

INPUT

DAC

STRING

DAC A

OUT

BUFFER

LDAC CLR POR

INPUT

DAC

STRING

DAC B

OUT

BUFFER

INPUT

DAC

STRING

DAC C

OUT

BUFFER

INPUT

DAC

STRING

DAC D

OUT

BUFFER

NOTES

1. THE FOLLOWING PINS ARE AVAILABLE ONLY ON 14-LEAD PACKAGE:

ADDR2, LDAC, CLR, POR.

06341-001

POWER-ON RESET POWER-DOWN LOGIC

6341-002

INTERFACE

LOGIC

SDA

SCL

ADDR1

ADDR2

GND

REFIN

AD5625/AD5665

INPUT

DAC

STRING

DAC A

OUT

BUFFER

LDAC CLR POR

INPUT

DAC

STRING

DAC B

OUT

BUFFER

INPUT

DAC

STRING

DAC C

OUT

BUFFER

INPUT

DAC

STRING

DAC D

OUT

BUFFER

NOTES

1. THE FOLLOWING PINS ARE AVAILABLE ONLY ON 14-LEAD PACKAGE:

ADDR2, LDAC, CLR, POR.

POWER-ON RESET POWER-DOWN LOGIC

Summary of content (36 pages)

PAGE 1
FEATURES FUNCTIONAL BLOCK DIAGRAMS VDD VREFIN/VREFOUT 1.25V/2.5V REF BUFFER ADDR1 INPUT REGISTER DAC REGISTER STRING DAC A INPUT REGISTER DAC REGISTER STRING DAC B INPUT REGISTER DAC REGISTER STRING DAC C INPUT REGISTER DAC REGISTER STRING DAC D VOUTA BUFFER ADDR2 SCL VOUTB BUFFER SDA VOUTC BUFFER POWER-ON RESET VOUTD POWER-DOWN LOGIC 06341-001 LDAC CLR POR NOTES 1. THE FOLLOWING PINS ARE AVAILABLE ONLY ON 14-LEAD PACKAGE: ADDR2, LDAC, CLR, POR. Figure 1.
PAGE 2
AD5625R/AD5645R/AD5665R, AD5625/AD5665 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 External Reference ..................................................................... 24 Applications ....................................................................................... 1 Serial Interface ............................................................................ 24 General Description ....................
PAGE 3
Data Sheet AD5625R/AD5645R/AD5665R, AD5625/AD5665 SPECIFICATIONS SPECIFICATIONS—AD5665R/AD5645R/AD5625R VDD = 2.7 V to 5.5 V; RL = 2 kΩ to GND; CL = 200 pF to GND; VREFIN = VDD; all specifications TMIN to TMAX, unless otherwise noted. Table 2.
PAGE 4
AD5625R/AD5645R/AD5665R, AD5625/AD5665 Parameter REFERENCE OUTPUT (1.25 V) Output Voltage Reference TC3 Output Impedance REFERENCE OUTPUT (2.5 V) Output Voltage Reference TC3 Output Impedance LOGIC INPUTS (ADDRx, CLR, LDAC, POR)3 IIN, Input Current VINL, Input Low Voltage VINH, Input High Voltage CIN, Pin Capacitance VHYST, Input Hysteresis LOGIC INPUTS (SDA, SCL)3 IIN, Input Current VINL, Input Low Voltage VINH, Input High Voltage CIN, Pin Capacitance VHYST, Input Hysteresis Min A Grade Typ Max 1.
PAGE 5
Data Sheet AD5625R/AD5645R/AD5665R, AD5625/AD5665 SPECIFICATIONS—AD5665/AD5625 VDD = 2.7 V to 5.5 V; RL = 2 kΩ to GND; CL = 200 pF to GND; VREFIN = VDD; all specifications TMIN to TMAX, unless otherwise noted. Table 3.
PAGE 6
AD5625R/AD5645R/AD5665R, AD5625/AD5665 Parameter LOGIC OUTPUTS (SDA)3 VOL, Output Low Voltage Floating-State Leakage Current Floating-State Output Capacitance POWER REQUIREMENTS VDD IDD (Normal Mode) 4 VDD = 4.5 V to 5.5 V VDD = 2.7 V to 3.6 V IDD (All Power-Down Modes) 5 VDD = 2.7 V to 5.5 V VDD = 3.6 V to 5.5 V Min B Grade Typ Max Data Sheet Unit Test Conditions/Comments 1 0.4 0.6 ±1 V V µA pF ISINK = 3 mA ISINK = 6 mA 5.5 V 1.0 0.9 1.16 1.05 mA mA 0.48 0.48 1 1 µA µA 2 2.
PAGE 7
Data Sheet AD5625R/AD5645R/AD5665R, AD5625/AD5665 AC CHARACTERISTICS VDD = 2.7 V to 5.5 V; RL = 2 kΩ to GND; CL = 200 pF to GND; VREFIN = VDD; all specifications TMIN to TMAX, unless otherwise noted. Table 4.
PAGE 8
AD5625R/AD5645R/AD5665R, AD5625/AD5665 Data Sheet I2C TIMING SPECIFICATIONS VDD = 2.7 V to 5.5 V; all specifications TMIN to TMAX, fSCL = 3.4 MHz, unless otherwise noted. 1 Table 5.
PAGE 9
Data Sheet Parameter t12 t13 t14 t15 tSP 4 AD5625R/AD5645R/AD5665R, AD5625/AD5665 Test Conditions 2 Standard mode Fast mode High speed mode, CB = 100 pF High speed mode, CB = 400 pF Standard mode Fast mode High speed mode Standard mode Min 10 20 10 10 10 300 Fast mode High speed mode Standard mode Fast mode High speed mode Fast mode High speed mode 300 30 20 20 20 0 0 Max 300 300 40 80 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 50 10 Description tFCL, fall time of SCL signal LDAC pulse
PAGE 10
AD5625R/AD5645R/AD5665R, AD5625/AD5665 Data Sheet ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 6. Parameter VDD to GND VOUT to GND VREFIN/VREFOUT to GND Digital Input Voltage to GND Operating Temperature Range, Industrial Storage Temperature Range Junction Temperature (TJ maximum) Power Dissipation θJA Thermal Impedance LFCSP_WD (4-Layer Board) TSSOP WLCSP Reflow Soldering Peak Temperature, RoHS Compliant Rating −0.3 V to +7 V −0.3 V to VDD + 0.3 V −0.3 V to VDD + 0.3 V −0.
PAGE 11
Data Sheet AD5625R/AD5645R/AD5665R, AD5625/AD5665 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS VOUTA 4 TOP VIEW (Not to Scale) VOUTC 5 POR 6 VREFIN/VREFOUT 7 SCL SDA VOUTA 1 12 GND VOUTB 2 GND 3 11 VOUTB 10 VOUTD VOUTC 4 9 CLR VOUTD 5 8 ADDR2 2 AD5625/ AD5665 VDD 3 VOUTA 4 TOP VIEW (Not to Scale) 14 SCL 13 SDA 12 GND 11 VOUTB 10 VOUTD POR 6 9 CLR VREFIN 7 8 ADDR2 VOUTC 5 9 VDD 8 SDA 7 SCL 6 ADDR Figure 6.
PAGE 12
AD5625R/AD5645R/AD5665R, AD5625/AD5665 BALL A1 INDICATOR 1 2 Data Sheet 3 VREFIN/ VREFOUT GND VOUTA VDD GND VOUTB SDA GND VOUTC A B C SCL ADDR VOUTD TOP VIEW (BALL SIDE DOWN) Not to Scale 06341-108 D Figure 8. Pin Configuration (12-Ball WLCSP) Table 8. Pin Function Descriptions Pin No. A1 Mnemonic VREFIN/VREFOUT A2, B2, C2 A3 B1 GND VOUTA VDD B3 C1 VOUTB SDA C3 D1 VOUTC SCL D2 ADDR D3 VOUTD Description The AD5665R has a common pin for reference input and reference output.
PAGE 13
Data Sheet AD5625R/AD5645R/AD5665R, AD5625/AD5665 TYPICAL PERFORMANCE CHARACTERISTICS 1.0 10 VDD = VREF = 5V TA = 25°C VDD = VREF = 5V TA = 25°C 0.8 6 0.6 4 0.4 DNL ERROR (LSB) 2 0 –2 –4 0.2 0 –0.2 –0.4 –6 –0.6 –8 –0.8 0 5k 10k 15k 20k 25k 30k 35k 40k 45k 50k 55k 60k 65k CODE –1.0 06341-005 –10 0 10k 40k 50k 60k 0.5 VDD = VREF = 5V TA = 25°C 3 30k CODE Figure 12. DNL, AD5665, External Reference Figure 9.
PAGE 14
AD5625R/AD5645R/AD5665R, AD5625/AD5665 Data Sheet 1.0 4 0.4 0 65000 CODE Figure 15. INL, AD5665R, 2.5 V Internal Reference 06341-013 60000 55000 50000 45000 40000 35000 0 65000 CODE 06341-010 60000 55000 50000 45000 40000 35000 –1.0 30000 –0.8 25000 –8 –10 20000 –0.6 15000 –0.4 –6 10000 –4 30000 –0.2 25000 0 –2 0.2 20000 2 10000 DNL ERROR (LSB) 0.6 0 VDD = 5V VREFOUT = 2.5V TA = 25°C 0.8 6 5000 INL ERROR (LSB) 8 15000 VDD = 5V VREFOUT = 2.
PAGE 15
Data Sheet AD5625R/AD5645R/AD5665R, AD5625/AD5665 1.0 0.4 0 65000 CODE Figure 21. INL, AD5665R,1.25 V Internal Reference 06341-019 60000 55000 0 65000 CODE 06341-016 60000 55000 50000 45000 40000 35000 30000 25000 20000 15000 –0.8 –1.0 5000 –8 –10 50000 –0.6 45000 –6 40000 –0.4 35000 –0.2 –4 30000 –2 0.2 25000 0 20000 2 15000 DNL ERROR (LSB) 0.6 4 10000 VDD = 3V VREFOUT = 1.25V TA = 25°C 0.8 6 0 INL ERROR (LSB) 8 10000 VDD = 3V VREFOUT = 1.
PAGE 16
AD5625R/AD5645R/AD5665R, AD5625/AD5665 Data Sheet 8 0 6 VDD = VREF = 5V VDD = 5V –0.02 MAX INL –0.04 GAIN ERROR 4 ERROR (% FSR) 2 MAX DNL 0 MIN DNL –2 –0.08 –0.10 –0.12 –0.14 –4 FULL-SCALE ERROR –0.16 MIN INL –6 –0.18 –20 0 20 40 60 TEMPERATURE (°C) 80 100 –0.20 –40 06341-022 –8 –40 –20 0 20 40 60 TEMPERATURE (°C) 80 100 06341-025 ERROR (LSB) –0.06 Figure 30. Gain Error and Full-Scale Error vs. Temperature Figure 27. INL Error and DNL Error vs. Temperature 10 1.
PAGE 17
Data Sheet AD5625R/AD5645R/AD5665R, AD5625/AD5665 1.0 2.0 TA = 25°C 1.8 VDD = 5.5V TA = 25°C 0.5 ZERO-SCALE ERROR 1.6 VREFOUT = 2.5V 1.4 IDD (mA) ERROR (mV) 0 –0.5 –1.0 1.2 VREFIN = 5V 1.0 0.8 0.6 –1.5 0.4 OFFSET ERROR 3.2 3.7 4.2 VDD (V) 4.7 5.2 0 512 06341-028 –2.5 2.7 0.2 10512 20512 50512 30512 40512 CODE 60512 06341-060 –2.0 Figure 36. Supply Current vs. DAC Code Figure 33. Zero-Scale Error and Offset Error vs. Supply 30 1.2 VDD = 3.6V 20 0.8 15 0.6 10 0.
PAGE 18
AD5625R/AD5645R/AD5665R, AD5625/AD5665 Data Sheet 0.5 0.4 DAC LOADED WITH FULL-SCALE SOURCING CURRENT DAC LOADED WITH ZERO-SCALE SINKING CURRENT ERROR VOLTAGE (V) 0.3 0.2 0.1 VDD = VREF = 5V TA = 25°C FULL-SCALE CODE CHANGE 0x0000 TO 0xFFFF OUTPUT LOADED WITH 2kΩ AND 200pF TO GND VDD = 3V VREFOUT = 1.25V 0 –0.1 –0.2 VOUT = 909mV/DIV VDD = 5V VREFOUT = 2.5V –0.3 1 –8 –6 –4 –2 0 2 CURRENT (mA) 4 6 8 10 06341-048 –0.5 –10 06341-031 –0.4 TIME BASE = 4µs/DIV Figure 42.
PAGE 19
VDD = VREF = 5V TA = 25°C DAC LOADED WITH MIDSCALE VDD = VREF = 5V TA = 25°C 5ns/SAMPLE NUMBER GLITCH IMPULSE = 9.494nV 1LSB CHANGE AROUND MIDSCALE (0x8000 TO 0x7FFF) 0 50 100 150 200 250 300 350 SAMPLE NUMBER 400 450 512 4s/DIV Figure 48. 0.1 Hz to 10 Hz Output Noise Plot, External Reference Figure 45. Digital-to-Analog Glitch Impulse (Negative) 2.498 1 VDD = 5V VREFOUT = 2.5V TA = 25°C DAC LOADED WITH MIDSCALE VDD = VREF = 5V TA = 25°C 5ns/SAMPLE NUMBER ANALOG CROSSTALK = 0.424nV 2.
PAGE 20
AD5625R/AD5645R/AD5665R, AD5625/AD5665 Data Sheet 16 800 TA = 25°C MIDSCALE LOADED 700 VREF = VDD TA = 25°C VDD = 3V 12 500 TIME (µs) OUTPUT NOISE (nV/√Hz) 14 600 400 10 300 VDD = 5V 8 VDD = 5V VREFOUT = 2.5V 200 6 1k 10k FREQUENCY (Hz) 100k 1M 4 06341-054 0 100 0 Figure 51. Noise Spectral Density, Internal Reference 3 4 5 6 7 CAPACITANCE (nF) 5 VDD = 5V TA = 25°C DAC LOADED WITH FULL SCALE VREF = 2V ± 0.
PAGE 21
Data Sheet AD5625R/AD5645R/AD5665R, AD5625/AD5665 TERMINOLOGY Relative Accuracy or Integral Nonlinearity (INL) For the DAC, relative accuracy or integral nonlinearity is a measurement of the maximum deviation, in LSBs, from a straight line passing through the endpoints of the DAC transfer function.
PAGE 22
AD5625R/AD5645R/AD5665R, AD5625/AD5665 Analog Crosstalk Analog crosstalk is the glitch impulse transferred to the output of one DAC due to a change in the output of another DAC. It is measured by loading one of the input registers with a full-scale code change (all 0s to all 1s and vice versa) and then executing a software LDAC and monitoring the output of the DAC whose digital code was not changed. The area of the glitch is expressed in nanovolts per second (nV-s).
PAGE 23
Data Sheet AD5625R/AD5645R/AD5665R, AD5625/AD5665 THEORY OF OPERATION DIGITAL-TO-ANALOG CONVERTER (DAC) RESISTOR STRING The AD56x5R/AD56x5 DACs are fabricated on a CMOS process. The AD56x5 does not have an internal reference, and the DAC architecture is shown in Figure 55. The AD56x5R does have an internal reference and can be configured for use with either an internal or external reference (see Figure 55 and Figure 56). The resistor string is shown in Figure 57.
PAGE 24
AD5625R/AD5645R/AD5665R, AD5625/AD5665 Data Sheet EXTERNAL REFERENCE The 2-wire serial bus protocol operates as follows: The VREFIN pin on the AD56x5R allows the use of an external reference if the application requires it. The default condition of the on-chip reference is off at power-up. All devices can be operated from a single 2.7 V to 5.5 V supply. 1. SERIAL INTERFACE The AD56x5R/AD56x5 have 2-wire I2C-compatible serial interfaces.
PAGE 25
Data Sheet AD5625R/AD5645R/AD5665R, AD5625/AD5665 1 9 1 9 SCL 0 SDA 0 0 1 1 A1 A0 R/W DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 ACK. BY AD56x5 START BY MASTER ACK. BY AD56x5 FRAME 2 COMMAND BYTE FRAME 1 SLAVE ADDRESS 1 9 1 9 SCL (CONTINUED) DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB7 DB8 DB6 DB5 ACK. BY AD56x5 FRAME 3 MOST SIGNIFICANT DATA BYTE DB4 DB3 DB2 DB1 DB0 ACK. BY STOP BY AD56x5 MASTER FRAME 4 LEAST SIGNIFICANT DATA BYTE 06341-103 SDA (CONTINUED) Figure 58.
PAGE 26
AD5625R/AD5645R/AD5665R, AD5625/AD5665 1 9 Data Sheet 1 9 SCL 0 SDA 0 1 A3 A2 A1 R/W A0 DB23 DB22 DB21 DB20 DB19 DB18 DB17 ACK. BY AD56x5 START BY MASTER DB16 ACK. BY MASTER FRAME 1 SLAVE ADDRESS FRAME 2 COMMAND BYTE 1 9 1 9 SCL (CONTINUED) DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB7 DB8 DB6 DB5 DB4 ACK. BY MASTER FRAME 3 MOST SIGNIFICANT DATA BYTE DB3 DB2 DB1 DB0 NO ACK. STOP BY MASTER FRAME 4 LEAST SIGNIFICANT DATA BYTE 06341-102 SDA (CONTINUED) Figure 61.
PAGE 27
AD5625R/AD5645R/AD5665R, AD5625/AD5665 BLOCK 1 BLOCK n BLOCK 2 S=0 S=0 S=0 SLAVE COMMAND MOST SIGNIFICANT LEAST SIGNIFICANT COMMAND MOST SIGNIFICANT LEAST SIGNIFICANT ADDRESS BYTE DATA BYTE DATA BYTE BYTE DATA BYTE DATA BYTE COMMAND MOST SIGNIFICANT LEAST SIGNIFICANT STOP BYTE DATA BYTE DATA BYTE Figure 63.
PAGE 28
AD5625R/AD5645R/AD5665R, AD5625/AD5665 Data Sheet BROADCAST MODE LDAC FUNCTION Broadcast addressing is supported on the AD56x5R/AD56x5 in write mode only. Broadcast addressing can be used to synchronously update or power down multiple AD56x5R/AD56x5 devices. When the broadcast address is used, the AD56x5R/ AD56x5 respond regardless of the states of the address pins. The AD56x5R/AD56x5 broadcast address is 00010000.
PAGE 29
Data Sheet AD5625R/AD5645R/AD5665R, AD5625/AD5665 Synchronous LDAC Table 13. LDAC Register Mode of Operation on the 10-Lead LFCSP (Load DAC Register) The DAC registers are updated after new data is read in. LDAC can be permanently low or pulsed. LDAC Bits (DB3 to DB0) 0 Asynchronous LDAC The outputs are not updated at the same time that the input registers are written to. When LDAC goes low, the DAC registers are updated with the contents of the input register.
PAGE 30
AD5625R/AD5645R/AD5665R, AD5625/AD5665 Data Sheet POWER-DOWN MODES Table 15. Modes of Operation for the AD56x5R/AD56x5 Command 100 is reserved for the power-up/power-down function. The power-up/power-down modes are programmed by setting Bit DB5 and Bit DB4. This defines the output state of the DAC amplifier, as shown in Table 15. Bit DB3 to Bit DB0 determine to which DAC or DACs the power-up/power-down command is applied.
PAGE 31
Data Sheet AD5625R/AD5645R/AD5665R, AD5625/AD5665 POWER-ON RESET AND SOFTWARE RESET Table 16. Software Reset Modes for the AD56x5R/AD56x5 The AD56x5R/AD56x5 contain a power-on reset circuit that controls the output voltage during power-up. The 10-lead version of the device powers up to 0 V. The 14-lead version has a power-on reset (POR) pin that allows the output voltage to be selected.
PAGE 32
AD5625R/AD5645R/AD5665R, AD5625/AD5665 Data Sheet APPLICATIONS INFORMATION R2 = 10kΩ USING A REFERENCE AS A POWER SUPPLY FOR THE AD56x5R/AD56x5 +5V 1 mA + (5 V/5 kΩ) = 2 mA 15V 5V VDD SCL SDA AD5625R/ AD5645R/ AD5665R/ AD5625/ AD5665 VOUT = 0V TO 5V GND 06341-043 2-WIRE SERIAL INTERFACE VOUT VDD +5V 10µF 0.1µF VO ±5V AD5625R/ AD5645R/ AD5665R/ AD5625/ AD5665 GND SCL –5V SDA 2-WIRE SERIAL INTERFACE Figure 74.
PAGE 33
Data Sheet AD5625R/AD5645R/AD5665R, AD5625/AD5665 OUTLINE DIMENSIONS 2.48 2.38 2.23 3.10 3.00 SQ 2.90 0.50 BSC 10 6 1.74 1.64 1.49 EXPOSED PAD 0.50 0.40 0.30 BOTTOM VIEW 0.80 0.75 0.70 SEATING PLANE 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.30 0.25 0.20 0.20 MIN 1 5 TOP VIEW PIN 1 INDICATOR (R 0.15) FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. 02-05-2013-C PIN 1 INDEX AREA 0.20 REF Figure 75.
PAGE 34
AD5625R/AD5645R/AD5665R, AD5625/AD5665 Data Sheet 1.705 1.665 1.625 BOTTOM VIEW (BALL SIDE UP) 3 2 1 A BALL A1 IDENTIFIER 2.285 2.245 2.205 1.50 REF B C D 0.50 BSC TOP VIEW (BALL SIDE DOWN) SEATING PLANE 0.380 0.355 0.330 END VIEW 1.00 REF COPLANARITY 0.05 0.340 0.320 0.300 0.270 0.240 0.210 Figure 77. 12-Ball Wafer Level Chip Scale Package [WLCSP] (CB-12-9) Dimensions shown in millimeters Rev. C | Page 34 of 36 08-31-2012-A 0.650 0.595 0.
PAGE 35
Data Sheet AD5625R/AD5645R/AD5665R, AD5625/AD5665 ORDERING GUIDE Model 1 AD5625BCPZ-R2 AD5625BCPZ-REEL7 AD5625BRUZ AD5625BRUZ-REEL7 AD5625RBCPZ-R2 AD5625RBCPZ-REEL7 AD5625RACPZ-REEL7 AD5625RACPZ-1RL7 AD5625RBRUZ-1 AD5625RBRUZ-1REEL7 AD5625RBRUZ-2 AD5625RBRUZ-2REEL7 AD5645RBCPZ-R2 AD5645RBCPZ-REEL7 AD5645RBRUZ AD5645RBRUZ-REEL7 AD5665BCPZ-R2 AD5665BCPZ-REEL7 AD5665BRUZ AD5665BRUZ-REEL7 AD5665RBCBZ-1-RL7 AD5665RBCPZ-R2 AD5665RBCPZ-REEL7 AD5665RBRUZ-1 AD5665RBRUZ-1REEL7 AD5665RBRUZ-2 AD5665RBRUZ-2REEL7 EVAL-
PAGE 36
AD5625R/AD5645R/AD5665R, AD5625/AD5665 NOTES I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors). ©2007-2013 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06341-0-3/13(C) Rev.