Datasheet

ManualsBrandsANALOG DEVICES ManualsData collecting ICsData acquisition IC - DA converter (DAC) LFCSP 10 WD

Dual, 12-/14-/16-Bit nanoDACs

with

5 ppm/°C On-Chip Reference, I

Interface

AD5627R/AD5647R/AD5667R, AD5627/AD5667

Rev. 0

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responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

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FEATURES

Low power, smallest pin-compatible, dual nanoDACs

AD5627R/AD5647R/AD5667R

12-/14-/16-bit

On-chip 1.25 V/2.5 V, 5 ppm/°C reference

AD5627/AD5667

12-/16-bit

External reference only

3 mm x 3 mm LFCSP and 10-lead MSOP

2.7 V to 5.5 V power supply

Guaranteed monotonic by design

Power-on reset to zero scale

Per channel power-down

Hardware

LDAC

and

CLR

functions

C-compatible serial interface supports standard (100 kHz),

fast (400 kHz), and high speed (3.4 MHz) modes

APPLICATIONS

Process control

Data acquisition systems

Portable battery-powered instruments

Digital gain and offset adjustment

Programmable voltage and current sources

Programmable attenuators

FUNCTIONAL BLOCK DIAGRAMS

INTERFACE

LOGIC

SDA

SCL

DDR

GND

POWER-ON

RESET

1.25V/2.5V REF

REFIN

REFOUT

AD5627R/AD5647R/AD5667R

POWER-DOWN

LOGIC

INPUT

DAC

STRING

DAC A

OUT

BUFFER

INPUT

DAC

STRING

DAC B

OUT

LDAC CLR

BUFFER

06342-001

Figure 1. AD5627R/AD5647R/AD5667R

INTERFACE

LOGIC

SDA

SCL

DDR

GND

POWER-ON

RESET

REFIN

AD5627/AD5667

POWER-DOWN

LOGIC

INPUT

DAC

STRING

DAC A

OUT

BUFFER

INPUT

DAC

STRING

DAC B

OUT

LDAC CLR

BUFFER

06342-002

Figure 2. AD5627/AD5667

GENERAL DESCRIPTION

The AD5627R/AD5647R/AD5667R, AD5627/AD5667

members of the nanoDAC family are low power, dual, 12-, 14-,

16-bit buffered voltage-out DACs with/without on-chip

reference. All devices operate from a single 2.7 V to 5.5 V

supply, are guaranteed monotonic by design, and have an I

C-

compatible serial interface.

The AD5627R/AD5647R/AD5667R have an on-chip reference.

The AD56x7RBCPZ have a 1.25 V, 5 ppm/°C reference, giving a

full-scale output range of 2.5 V; the AD56x7RBRMZ have a

2.5 V, 5 ppm/°C reference, giving a full-scale output range of 5

V. The on-chip reference is off at power-up, allowing the use of

an external reference. The internal reference is enabled via a

software write. The AD5667 and AD5627 require an external

reference voltage to set the output range of the DAC.

The AD56x7R/AD56x7 incorporate a power-on reset circuit

that ensures the DAC output powers up to 0 V, and remains

there until a valid write takes place. The part contains a per-

channel power-down feature that reduces the current

consumption of the device to 480 nA at 5 V and provides

software-selectable output loads while in power-down mode.

The low power consumption of this part in normal operation

makes it ideally suited to portable battery-operated equipment.

The on-chip precision output amplifier enables rail-to-rail

output swing.

The AD56x7R/AD56x7 use a 2-wire I

C-compatible serial

interface that operates in standard (100 kHz), fast (400 kHz),

and high speed (3.4 MHz) modes.

Table 1. Related Devices

Part No. Description

AD5663 2.7 V to 5.5 V, dual 16-bit DAC,

external reference, SPI® interface

AD5623R/AD5643R/AD5663R 2.7 V to 5.5 V, dual 12-, 14-, 16-bit

DACs, internal reference,

SPI interface

AD5625R/AD5645R/AD5665R,

AD5625/AD5665

2.7 V to 5.5 V, quad 12-, 14-, 16-bit

DACs, with/without internal

reference, I

C interface

Summary of content (32 pages)

PAGE 1
Dual, 12-/14-/16-Bit nanoDACs® with 5 ppm/°C On-Chip Reference, I2C® Interface AD5627R/AD5647R/AD5667R, AD5627/AD5667 FEATURES Process control Data acquisition systems Portable battery-powered instruments Digital gain and offset adjustment Programmable voltage and current sources Programmable attenuators VDD GND VREFIN/VREFOUT AD5627R/AD5647R/AD5667R 1.25V/2.
PAGE 2
AD5627R/AD5647R/AD5667R, AD5627/AD5667 TABLE OF CONTENTS Features .............................................................................................. 1 Serial Interface ............................................................................ 21 Applications....................................................................................... 1 Write Operation.......................................................................... 21 Functional Block Diagrams............................
PAGE 3
AD5627R/AD5647R/AD5667R, AD5627/AD5667 SPECIFICATIONS VDD = 2.7 V to 5.5 V; RL = 2 kΩ to GND; CL = 200 pF to GND; VREFIN = VDD; all specifications TMIN to TMAX, unless otherwise noted. Table 2.
PAGE 4
AD5627R/AD5647R/AD5667R, AD5627/AD5667 Parameter LOGIC INPUTS (ADDR, CLR, LDAC)3 IIN, Input Current VINL, Input Low Voltage VINH, Input High Voltage CIN, Pin Capacitance Min VHYST, Input Hysteresis LOGIC INPUTS (SDA, SCL) IIN, Input Current VINL, Input Low Voltage VINH, Input High Voltage CIN, Pin Capacitance VHYST, Input Hysteresis LOGIC OUTPUTS (OPEN-DRAIN) VOL, Output Low Voltage 0.
PAGE 5
AD5627R/AD5647R/AD5667R, AD5627/AD5667 AC CHARACTERISTICS VDD = 2.7 V to 5.5 V; RL = 2 kΩ to GND; CL = 200 pF to GND; VREFIN = VDD; all specifications TMIN to TMAX, unless otherwise noted. 1 Table 3.
PAGE 6
AD5627R/AD5647R/AD5667R, AD5627/AD5667 I2C TIMING SPECIFICATIONS VDD = 2.7 V to 5.5 V; all specifications TMIN to TMAX, fSCL = 3.4 MHz, unless otherwise noted.1 Table 4.
PAGE 7
AD5627R/AD5647R/AD5667R, AD5627/AD5667 Parameter t12 t13 t14 t15 tSP4 Conditions2 Standard mode Fast mode High speed mode, CB = 100 pF High speed mode, CB = 400 pF Standard mode Fast mode High speed mode Standard mode 10 20 10 10 10 300 Fast mode High speed mode Standard mode Fast mode High speed mode Fast mode High speed mode 300 30 20 20 20 0 0 Min Max 300 300 40 80 Unit ns ns ns ns ns ns ns ns Description tFCL, fall time of SCL signal LDAC pulse width low Falling edge of 9th SCL clock pulse
PAGE 8
AD5627R/AD5647R/AD5667R, AD5627/AD5667 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 5. Parameter VDD to GND VOUT to GND VREFIN/VREFOUT to GND Digital Input Voltage to GND Operating Temperature Range, Industrial Storage Temperature Range Junction Temperature (TJ maximum) Power Dissipation θJA Thermal Impedance LFCSP_WD Package (4-Layer Board) MSOP Package Reflow Soldering Peak Temperature, Pb-Free Rating −0.3 V to +7 V −0.3 V to VDD + 0.3 V −0.3 V to VDD + 0.3 V −0.3 V to VDD + 0.
PAGE 9
AD5627R/AD5647R/AD5667R, AD5627/AD5667 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS GND 3 LDAC 4 CLR 5 AD5627/ AD5667 TOP VIEW (Not to Scale) 10 VREFIN VOUTA 1 9 VDD VOUTB 2 8 SDA GND 3 7 SCL LDAC 4 6 ADDR EXPOSED PAD TIED TO GND ON LFCSP PACKAGE. CLR 5 AD5627R/ AD5647R/ AD5667R TOP VIEW (Not to Scale) 10 VREFIN/VREFOUT 9 VDD 8 SDA 7 SCL 6 ADDR EXPOSED PAD TIED TO GND ON LFCSP PACKAGE. Figure 4. AD5627/AD5667 Pin Configuration 06342-102 VOUTB 2 06342-101 VOUTA 1 Figure 5.
PAGE 10
AD5627R/AD5647R/AD5667R, AD5627/AD5667 TYPICAL PERFORMANCE CHARACTERISTICS 8 0.6 4 0.4 DNL ERROR (LSB) 6 2 0 –2 –4 0.2 0 –0.2 –0.4 –6 –0.6 –8 –0.8 –10 0 VDD = VREF = 5V TA = 25°C 0.8 5k 10k 15k 20k 25k 30k 35k 40k 45k 50k 55k 60k 65k CODE –1.0 06342-005 INL ERROR (LSB) 1.0 VDD = VREF = 5V TA = 25°C 0 10k 50k 60k VDD = VREF = 5V TA = 25°C 0.4 0.3 DNL ERROR (LSB) 2 INL ERROR (LSB) 40k 0.5 VDD = VREF = 5V TA = 25°C 3 30k CODE Figure 9.
PAGE 11
AD5627R/AD5647R/AD5667R, AD5627/AD5667 1.0 0.6 65000 06342-013 60000 55000 50000 CODE Figure 15. AD5667R DNL, 2.5 V Internal Reference Figure 12. AD5667R INL, 2.5 V Internal Reference 4 0.5 VDD = 5V VREFOUT = 2.5V TA = 25°C 3 VDD = 5V VREFOUT = 2.5V TA = 25°C 0.4 0.3 DNL ERROR (LSB) 2 INL ERROR (LSB) 45000 0 65000 CODE 06342-010 60000 55000 50000 45000 40000 35000 30000 25000 20000 15000 –1.0 5000 –0.8 10000 –8 –10 0 –0.6 40000 –0.4 –6 35000 –4 0 –0.
PAGE 12
AD5627R/AD5647R/AD5667R, AD5627/AD5667 1.0 0.6 –0.2 65000 CODE Figure 18. AD5667R INL,1.25 V Internal Reference 06342-019 60000 55000 50000 0 65000 CODE 06342-016 60000 55000 50000 45000 40000 35000 30000 25000 20000 –1.0 15000 –0.8 10000 –8 –10 0 –0.6 5000 –6 45000 –0.4 40000 –4 0 35000 –2 0.2 30000 0 25000 2 0.4 20000 4 DNL ERROR (LSB) INL ERROR (LSB) 6 VDD = 3V VREFOUT = 1.25V TA = 25°C 0.8 5000 8 15000 VDD = 3V VREFOUT = 1.
PAGE 13
AD5627R/AD5647R/AD5667R, AD5627/AD5667 8 0 6 VDD = VREF = 5V VDD = 5V –0.02 MAX INL –0.04 GAIN ERROR 4 ERROR (% FSR) 2 MAX DNL 0 MIN DNL –2 –0.08 –0.10 –0.12 –0.14 –4 FULL-SCALE ERROR –0.16 MIN INL –6 –0.18 –20 0 20 40 60 TEMPERATURE (°C) 80 100 –0.20 –40 06342-022 –8 –40 Figure 24. INL Error and DNL Error vs. Temperature –20 0 20 40 60 TEMPERATURE (°C) 80 100 06342-025 ERROR (LSB) –0.06 Figure 27. Gain Error and Full-Scale Error vs. Temperature 10 1.5 MAX INL 8 1.
PAGE 14
AD5627R/AD5647R/AD5667R, AD5627/AD5667 0.5 1.0 TA = 25°C 0.4 ZERO-SCALE ERROR ERROR VOLTAGE (V) –0.5 –1.0 –1.5 0.2 0.1 VDD = 3V VREFOUT = 1.25V 0 –0.1 –0.2 VDD = 5V VREFOUT = 2.5V –0.3 –2.0 OFFSET ERROR 3.2 3.7 4.2 VDD (V) 4.7 5.2 –0.4 –0.5 –10 06342-028 –2.5 2.7 Figure 30. Zero-Scale Error and Offset Error vs. Supply 18 –8 –6 –4 4 6 8 10 6 VDD = 5.5V 5 VDD = 5V VREFOUT = 2.
PAGE 15
AD5627R/AD5647R/AD5667R, AD5627/AD5667 0.9 TA = 25°C 0.8 VDD = 5V, VREFOUT = 2.5V 0.7 VDD = VREF = 5V TA = 25°C FULL-SCALE CODE CHANGE 0x0000 TO 0xFFFF OUTPUT LOADED WITH 2kΩ AND 200pF TO GND IDD (mA) 0.6 0.5 VDD = VREF = 5V 0.4 0.3 VOUT = 909mV/DIV 0.2 1 10512 20512 30512 40512 CODE 50512 60512 06342-048 0 512 06342-060 0.1 TIME BASE = 4µs/DIV Figure 39. Full-Scale Settling Time, 5 V Figure 36. Supply Current vs. Code 0.40 VDD = VREF = 5V TA = 25°C 0.35 0.30 0.20 VDD 1 0.15 0.
PAGE 16
VDD = VREF = 5V TA = 25°C DAC LOADED WITH MIDSCALE VDD = VREF = 5V TA = 25°C 5ns/SAMPLE NUMBER GLITCH IMPULSE = 9.494nV 1LSB CHANGE AROUND MIDSCALE (0x8000 TO 0x7FFF) 0 50 100 150 200 250 300 350 SAMPLE NUMBER 400 450 512 4s/DIV Figure 45. 0.1 Hz to 10 Hz Output Noise Plot, External Reference Figure 42. Digital-to-Analog Glitch Impulse (Negative) 2.498 1 VDD = 5V VREFOUT = 2.5V TA = 25°C DAC LOADED WITH MIDSCALE VDD = VREF = 5V TA = 25°C 5ns/SAMPLE NUMBER ANALOG CROSSTALK = 0.424nV 2.
PAGE 17
AD5627R/AD5647R/AD5667R, AD5627/AD5667 800 16 TA = 25°C MIDSCALE LOADED VREF = VDD TA = 25°C 14 600 VDD = 3V 12 TIME (µs) 500 400 300 1k 10k FREQUENCY (Hz) 100k 1M 4 0 Figure 48. Noise Spectral Density, Internal Reference –30 4 5 6 7 CAPACITANCE (nF) 5 VDD = 5V TA = 25°C DAC LOADED WITH FULL SCALE VREF = 2V ± 0.3V p-p 8 9 10 VDD = 5V TA = 25°C 0 –5 –10 (dB) –50 –60 –70 –15 –20 –25 –80 –30 –90 –35 2k 4k 6k FREQUENCY (Hz) 8k 10k 06342-055 (dB) 3 Figure 50.
PAGE 18
AD5627R/AD5647R/AD5667R, AD5627/AD5667 TERMINOLOGY Relative Accuracy or Integral Nonlinearity (INL) For the DAC, relative accuracy or integral nonlinearity is a measurement of the maximum deviation, in LSBs, from a straight line passing through the endpoints of the DAC transfer function. Differential Nonlinearity (DNL) Differential nonlinearity is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes.
PAGE 19
AD5627R/AD5647R/AD5667R, AD5627/AD5667 Analog Crosstalk Analog crosstalk is the glitch impulse transferred to the output of one DAC due to a change in the output of another DAC. It is measured by loading one of the input registers with a full-scale code change (all 0s to all 1s and vice versa), then executing a software LDAC and monitoring the output of the DAC whose digital code was not changed. The area of the glitch is expressed in nV-s.
PAGE 20
AD5627R/AD5647R/AD5667R, AD5627/AD5667 THEORY OF OPERATION D/A SECTION R The AD56x7R/AD56x7 DACs are fabricated on a CMOS process. The architecture consists of a string DAC followed by an output buffer amplifier. Figure 52 shows a block diagram of the DAC architecture. R REF (+) DAC REGISTER TO OUTPUT AMPLIFIER R OUTPUT AMPLIFIER GAIN = +2 RESISTOR STRING REF (–) GND VOUT R 06342-032 VDD R 06342-033 Figure 52.
PAGE 21
AD5627R/AD5647R/AD5667R, AD5627/AD5667 SERIAL INTERFACE WRITE OPERATION 2 The AD56x7R/AD56x7 have 2-wire I C-compatible serial interfaces (refer to I2C-Bus Specification, Version 2.1, January 2000, available from Philips Semiconductor). The AD56x7R/AD56x7 can be connected to an I2C bus as a slave device, under the control of a master device. See Figure 3 for a timing diagram of a typical write sequence. The AD56x7R/AD56x7 support standard (100 kHz), fast (400 kHz), and high speed (3.
PAGE 22
AD5627R/AD5647R/AD5667R, AD5627/AD5667 1 9 1 9 SCL 0 SDA 0 0 1 1 A1 R/W A0 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 ACK. BY AD56x7 START BY MASTER ACK. BY AD56x7 FRAME 1 SLAVE ADDRESS FRAME 2 COMMAND BYTE 1 9 9 1 SCL (CONTINUED) DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB7 DB8 DB6 DB5 DB4 ACK. BY AD56x7 FRAME 3 MOST SIGNIFICANT DATA BYTE DB3 DB2 DB1 DB0 ACK. BY STOP BY AD56x7 MASTER FRAME 4 LEAST SIGNIFICANT DATA BYTE 06342-103 SDA (CONTINUED) Figure 54.
PAGE 23
AD5627R/AD5647R/AD5667R, AD5627/AD5667 INPUT SHIFT REGISTER Table 9. DAC Address Command The input shift register is 24 bits wide. Data is loaded into the device as a 24-bit word under the control of a serial clock input, SCL. The timing diagram for this operation is shown in Figure 3. The 8 MSBs make up the command byte. DB23 is reserved and should always be set to 0 when writing to the device.
PAGE 24
AD5627R/AD5647R/AD5667R, AD5627/AD5667 BLOCK 2 BLOCK n S=1 S=1 SLAVE COMMAND MOST SIGNIFICANT LEAST SIGNIFICANT MOST SIGNIFICANT LEAST SIGNIFICANT ADDRESS BYTE DATA BYTE DATA BYTE DATA BYTE DATA BYTE MOST SIGNIFICANT LEAST SIGNIFICANT STOP DATA BYTE DATA BYTE 06342-106 BLOCK 1 S=1 Figure 57.
PAGE 25
AD5627R/AD5647R/AD5667R, AD5627/AD5667 Synchronous LDAC amplifier, as shown in Table 11. Bit DB1and Bit DB0 determine to which DAC or DACs the power-up/down command is applied. Setting one of these bits to 1 applies the power-up/down state defined by DB5 and DB4 to the corresponding DAC. If a bit is 0, the state of the DAC is unchanged. Figure 65 shows the contents of the input shift register for the power up/down command. The DAC registers are updated after new data is read in.
PAGE 26
AD5627R/AD5647R/AD5667R, AD5627/AD5667 POWER-ON RESET AND SOFTWARE RESET CLEAR PIN (CLR) The AD56x7R/AD56x7 contain a power-on reset circuit that controls the output voltage during power-up. The device powers up to 0 V and the output remains powered up at this level until a valid write sequence is made to the DAC. This is useful in applications where it is important to know the state of the output of the DAC while it is in the process of powering up.
PAGE 27
AD5627R/AD5647R/AD5667R, AD5627/AD5667 APPLICATION INFORMATION R2 = 10kΩ USING A REFERENCE AS A POWER SUPPLY FOR THE AD56x7R/AD56x7 +5V R1 = 10kΩ The load regulation of the REF195 is typically 2 ppm/mA, resulting in a 2.9 ppm (14.5 μV) error for the 1.45 mA current drawn from it. This corresponds to a 0.191 LSB error. 15V 5V VDD SCL SDA AD5627R/ AD5647R/ AD5667R/ AD5627/ AD5667 VOUT = 0V TO 5V GND 06342-043 2-WIRE SERIAL INTERFACE VDD +5V 10µF 0.
PAGE 28
AD5627R/AD5647R/AD5667R, AD5627/AD5667 OUTLINE DIMENSIONS INDEX AREA PIN 1 INDICATOR 3.00 BSC SQ 10 1.50 BCS SQ 0.50 BSC 1 (BOTTOM VIEW) 6 0.80 MAX 0.55 TYP 0.80 0.75 0.70 5 0.50 0.40 0.30 1.74 1.64 1.49 0.05 MAX 0.02 NOM SIDE VIEW SEATING PLANE 2.48 2.38 2.23 EXPOSED PAD TOP VIEW 0.30 0.23 0.18 0.20 REF Figure 69. 10-Lead Lead Frame Chip Scale Package [LFCSP_WD] 3 mm x 3 mm Body, Very Very Thin, Dual Lead (CP-10-9) Dimensions shown in millimeters 3.10 3.00 2.90 10 3.10 3.00 2.
PAGE 29
AD5627R/AD5647R/AD5667R, AD5627/AD5667 ORDERING GUIDE Model AD5627BCPZ-R2 1 AD5627BCPZ-REEL71 AD5627BRMZ1 AD5627BRMZ-REEL71 AD5627RBCPZ-R21 AD5627RBCPZ-REEL71 AD5627RBRMZ-11 AD5627RBRMZ-1REEL71 AD5627RBRMZ-21 AD5627RBRMZ-2REEL71 AD5647RBCPZ-R21 AD5647RBCPZ-REEL71 AD5647RBRMZ1 AD5647RBRMZ-REEL71 AD5667BCPZ-R21 AD5667BCPZ-REEL71 AD5667BRMZ1 AD5667BRMZ-REEL71 AD5667RBCPZ-R21 AD5667RBCPZ-REEL71 AD5667RBRMZ-11 AD5667RBRMZ-1REEL71 AD5667RBRMZ-21 AD5667RBRMZ-2REEL71 EVAL-AD5667REBZ1 1 Temperature Range −40°C to +
PAGE 30
AD5627R/AD5647R/AD5667R, AD5627/AD5667 NOTES Rev.
PAGE 31
AD5627R/AD5647R/AD5667R, AD5627/AD5667 NOTES Rev.
PAGE 32
AD5627R/AD5647R/AD5667R, AD5627/AD5667 NOTES Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. ©2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06342-0-1/07(0) Rev.