Quad-Channel, 12-Bit, Serial Input, 4 mA to 20 mA Output DAC with Dynamic Power Control and HART Connectivity AD5737 Data Sheet Each channel has a corresponding CHART pin so that HART signals can be coupled onto the current output of the AD5737. FEATURES 12-bit resolution and monotonicity Dynamic power control for thermal management or external PMOS mode Current output ranges: 0 mA to 20 mA, 4 mA to 20 mA, and 0 mA to 24 mA ±0.
AD5737 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Readback Operation .................................................................. 31 Applications ....................................................................................... 1 Device Features ............................................................................... 33 General Description .....................................................
Data Sheet AD5737 REVISION HISTORY 11/12—Rev. C to Rev. D 11/11—Rev. 0 to Rev. A Changed Thermal Impedance from 20°C/W to 28°C/W. .........10 Changes to Pin 6 Description ........................................................11 Changes to DUT_AD1, DUT_AD0 Description, Table 11 .......26 Changes to Changes to Packet Error Checking Section and Internal Reference Section .............................................................34 Changes to Figure 56 ..................................................
AD5737 Data Sheet DETAILED FUNCTIONAL BLOCK DIAGRAM AV CC 5.0V AGND DVDD DGND LDAC CLEAR SCLK SDIN SYNC SDO INPUT SHIFT REGISTER AND CONTROL VBOOST_A DC-TO-DC CONVERTER DYNAMIC POWER CONTROL STATUS REGISTER REFOUT SWA POWER-ON RESET FAULT ALERT AV DD +15V 12 DAC DATA REG A + DAC INPUT REG A 12 7.4V TO 29.
Data Sheet AD5737 SPECIFICATIONS AVDD = VBOOST_x = 15 V; DVDD = 2.7 V to 5.5 V; AVCC = 4.5 V to 5.5 V; dc-to-dc converter disabled; AGND = DGND = GNDSWx = 0 V; REFIN = 5 V; RL = 300 Ω; all specifications TMIN to TMAX, unless otherwise noted. Table 1.
AD5737 Parameter 1 Output Noise (0.1 Hz to 10 Hz)2 Noise Spectral Density2 Output Voltage Drift vs.
Data Sheet AD5737 AC PERFORMANCE CHARACTERISTICS AVDD = VBOOST_x = 15 V; DVDD = 2.7 V to 5.5 V; AVCC = 4.5 V to 5.5 V; dc-to-dc converter disabled; AGND = DGND = GNDSWx = 0 V; REFIN = 5 V; RL = 300 Ω; all specifications TMIN to TMAX, unless otherwise noted. Table 2. Parameter 1 DYNAMIC PERFORMANCE, CURRENT OUTPUT Output Current Settling Time Min Max 15 See Test Conditions/Comments Output Noise (0.
AD5737 Data Sheet Timing Diagrams t1 SCLK 1 2 24 t3 t6 t2 t4 t5 SYNC t8 t7 SDIN t19 LSB MSB t10 t10 t9 LDAC t17 t12 t11 IOUT_x LDAC = 0 t12 t16 IOUT_x t13 CLEAR t14 IOUT_x 10067-002 t18 RESET Figure 3. Serial Interface Timing Diagram SCLK 1 1 24 24 t6 SYNC MSB LSB MSB LSB INPUT WORD SPECIFIES REGISTER TO BE READ NOP CONDITION MSB SDO LSB UNDEFINED t15 Figure 4. Readback Timing Diagram Rev.
Data Sheet LSB 1 AD5737 MSB 16 2 SCLK SDO R/W DUT_ AD1 DUT_ AD0 SDO DISABLED X X X D15 D14 D1 D0 SDO_ ENAB STATUS STATUS STATUS STATUS Figure 5. Status Readback During Write, Timing Diagram 200µA TO OUTPUT PIN IOL VOH (MIN) OR VOL (MAX) CL 50pF 200µA IOH Figure 6. Load Circuit for SDO Timing Diagrams Rev.
AD5737 Data Sheet ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Transient currents of up to 100 mA do not cause SCR latch-up. Table 4. Parameter AVDD, VBOOST_x to AGND, DGND AVCC to AGND DVDD to DGND Digital Inputs to DGND Digital Outputs to DGND REFIN, REFOUT to AGND IOUT_x to AGND SWx to AGND AGND, GNDSWx to DGND Operating Temperature Range (TA) Industrial1 Storage Temperature Range Junction Temperature (TJ max) Power Dissipation Lead Temperature Soldering 1 Rating −0.3 V to +33 V −0.
Data Sheet AD5737 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 RSET_C RSET_D REFOUT REFIN NC CHARTD IGATED COMPDCDC_D VBOOST_D NC IOUT_D AGND NC CHARTC NC IGATEC PIN CONFIGURATION AND FUNCTION DESCRIPTIONS PIN 1 INDICATOR 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 AD5737 TOP VIEW (Not to Scale) 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 COMPDCDC_C IOUT_C VBOOST_C AV CC SWC GNDSWC GNDSWD SWD AGND SWA GNDSWA GNDSWB SWB AGND VBOOST_B IOUT_B NOTES 1. NC = NO CONNECT. DO NOT CONNECT TO THIS PIN. 2.
AD5737 Data Sheet Pin No. 14 Mnemonic CLEAR 15 ALERT 16 FAULT 17 18 19 20 21 22 DGND RESET AVDD NC CHARTA IGATEA 23 COMPDCDC_A 24 VBOOST_A 25 26 27 28 29 30 31 NC IOUT_A AGND NC CHARTB NC IGATEB 32 COMPDCDC_B 33 34 IOUT_B VBOOST_B 35 36 AGND SWB 37 38 39 GNDSWB GNDSWA SWA 40 41 AGND SWD 42 43 44 GNDSWD GNDSWC SWC 45 46 AVCC VBOOST_C 47 48 IOUT_C COMPDCDC_C Description Active High, Edge Sensitive Input.
Data Sheet Pin No. 49 Mnemonic IGATEC 50 51 52 53 54 55 56 NC CHARTC NC AGND IOUT_D NC VBOOST_D 57 COMPDCDC_D 58 IGATED 59 60 61 62 CHARTD NC REFIN REFOUT 63 RSET_D 64 RSET_C EPAD AD5737 Description Optional Connection for External Pass Transistor. Leave this pin unconnected when using the dc-to-dc converter. For more information, see the External PMOS Mode section. No Connect. Do not connect to this pin. HART Input Connection for DAC Channel C.
AD5737 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS CURRENT OUTPUTS 0.008 0.008 4mA TO 20mA, INTERNAL RSET, WITH DC-TO-DC CONVERTER 4mA TO 20mA, EXTERNAL RSET, WITH DC-TO-DC CONVERTER 4mA TO 20mA, INTERNAL RSET 4mA TO 20mA, EXTERNAL RSET 0.006 0.006 0.004 INL ERROR (%FSR) 0.002 0 –0.002 0.002 0 –0.002 4mA TO 20mA RANGE MAX INL 0mA TO 24mA RANGE MAX INL 0mA TO 20mA RANGE MAX INL 4mA TO 20mA RANGE MIN INL 0mA TO 24mA RANGE MIN INL 0mA TO 20mA RANGE MIN INL AVDD = 15V –0.
Data Sheet AD5737 0.008 0.025 MAX INL 0.006 0.015 0.005 0 –0.005 AV DD = 15V –0.010 0.004 INL ERROR (%FSR) 0.010 4mA TO 20mA RANGE TA = 25°C 0.002 0 –0.002 –0.015 –0.004 –0.025 –40 –20 0 20 40 60 TEMPERATURE (°C) 80 100 –0.006 MIN INL 5 10 15 20 25 30 SUPPLY (V) Figure 14. Total Unadjusted Error vs. Temperature 10067-240 4mA TO 20mA RANGE, INTERNAL R SET 4mA TO 20mA RANGE, EXTERNAL R SET –0.020 10067-155 TOTAL UNADJUSTED ERROR (%FSR) 0.020 Figure 17.
AD5737 Data Sheet 6 AV DD = 15V TA = 25°C RLOAD = 300Ω MAX TUE 0 5 –0.005 4 CURRENT (µA) 4mA TO 20mA RANGE TA = 25°C –0.010 –0.015 –0.020 3 2 MIN TUE –0.025 1 –0.035 5 10 15 20 25 30 SUPPLY (V) 0 0 5 Figure 20. Total Unadjusted Error vs. Supply, External RSET 20 4 0.06 MAX TUE 2 0.05 0 4mA TO 20mA RANGE TA = 25°C 0.02 0.01 –2 –4 –6 0 –8 –0.01 –0.02 5 10 15 20 25 30 SUPPLY (V) –10 0 0.002 0 –0.
Data Sheet AD5737 10 30 20mA OUTPUT 10mA OUTPUT 8 TA = –40°C TA = +25°C TA = +105°C 15 10 0mA TO 24mA RANGE 1kΩ LOAD fSW = 410kHz INDUCTOR = 10µH (XAL4040-103) AV CC = 5V 5 0 0.25 0.50 0.75 1.00 1.25 1.50 4 2 0 –2 –4 –6 AV CC = 5V fSW = 410kHz INDUCTOR = 10µH (XAL4040-103) –8 1.75 –10 TIME (ms) 0 2 4 6 0mA TO 24mA RANGE 1kΩ LOAD fSW = 410kHz INDUCTOR = 10µH (XAL4040-103) TA = 25°C HEADROOM VOLTAGE (V) 25 20 AV CC = 4.5V AV CC = 5.0V AV CC = 5.
AD5737 Data Sheet DC-TO-DC CONVERTER 80 90 AV CC = 4.5V AV CC = 5V AV CC = 5.5V 85 20mA OUTPUT 70 75 70 65 0mA TO 24mA RANGE 1kΩ LOAD EXTERNAL RSET fSW = 410kHz INDUCTOR = 10µH (XAL4040-103) TA = 25°C 55 50 0 4 8 12 16 20 50 40 30 24 OUTPUT CURRENT (mA) 20 –40 10067-016 60 60 0mA TO 24mA RANGE 1kΩ LOAD EXTERNAL RSET AV CC = 5V fSW = 410kHz INDUCTOR = 10µH (XAL4040-103) –20 0 20 40 60 80 100 TEMPERATURE (°C) Figure 32. Efficiency at VBOOST_x vs.
Data Sheet AD5737 REFERENCE 5.0050 16 AV DD REFOUT TA = 25°C 12 8 6 4 2 0 5.0035 5.0030 5.0025 5.0020 5.0015 5.0010 0.2 0.4 0.6 0.8 1.0 1.2 TIME (ms) 5.0000 –40 10067-010 0 Figure 37. REFOUT Voltage Turn-On Transient –20 0 20 40 60 80 100 TEMPERATURE (°C) 10067-163 5.0005 –2 Figure 40. REFOUT Voltage vs. Temperature (When the AD5737 is soldered onto a PCB, the reference shifts due to thermal shock on the package. The average output voltage shift is −4 mV.
AD5737 Data Sheet GENERAL 450 13.4 DVDD = 5V TA = 25°C 400 13.3 350 FREQUENCY (MHz) 13.2 250 200 150 13.0 12.9 12.8 12.7 50 0 1 2 3 4 5 SDIN VOLTAGE (V) 12.6 –40 10067-007 0 –20 0 20 40 60 80 100 TEMPERATURE (°C) Figure 43. DICC vs. Logic Input Voltage Figure 45. Internal Oscillator Frequency vs. Temperature 8 14.4 7 14.2 6 FREQUENCY (MHz) 14.0 5 4 3 13.8 13.6 13.4 2 AIDD TA = 25°C IOUT = 0mA 15 20 25 30 VOLTAGE (V) 13.2 TA = 25°C 10067-009 1 0 10 DVDD = 5.
Data Sheet AD5737 TERMINOLOGY Relative Accuracy or Integral Nonlinearity (INL) Relative accuracy, or integral nonlinearity (INL), is a measure of the maximum deviation from the best fit line through the DAC transfer function. INL is expressed in percent of full-scale range (% FSR). A typical INL vs. code plot is shown in Figure 8. Differential Nonlinearity (DNL) Differential nonlinearity (DNL) is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes.
AD5737 Data Sheet THEORY OF OPERATION The AD5737 is a quad, precision digital-to-current loop converter designed to meet the requirements of industrial process control applications. It provides a high precision, fully integrated, low cost, single-chip solution for generating current loop outputs. The current ranges available are 0 mA to 20 mA, 4 mA to 20 mA, and 0 mA to 24 mA. The output configuration is user-selectable via the DAC control register.
Data Sheet AD5737 TRANSFER FUNCTION For the 4 mA to 20 mA range For the 0 mA to 20 mA, 0 mA to 24 mA, and 4 mA to 20 mA current output ranges, the output current is expressed by the following equations: For the 0 mA to 20 mA range 20 mA I OUT = N × D 2 16 mA I OUT = N × D + 4 mA 2 where: D is the decimal equivalent of the code loaded to the DAC. N is the bit resolution of the DAC. For the 0 mA to 24 mA range 24 mA I OUT = N × D 2 Rev.
AD5737 Data Sheet REGISTERS Table 7, Table 8, and Table 9 provide an overview of the registers for the AD5737. Table 7. Data Registers for the AD5737 Register DAC Data Registers Gain Registers Offset Registers Clear Code Registers Description The four DAC data registers (one register per DAC channel) are used to write a DAC code to each DAC channel. The DAC data bits are D15 to D4. The four gain registers (one register per DAC channel) are used to program the gain trim on a per-channel basis.
Data Sheet AD5737 ENABLING THE OUTPUT REPROGRAMMING THE OUTPUT RANGE To correctly write to and set up the part from a power-on condition, use the following sequence: When changing the range of an output, the same sequence described in the Enabling the Output section should be used. It is recommended that the range be set to 0 V (zero scale or midscale) before the output is disabled.
AD5737 Data Sheet DATA REGISTERS DAC Data Register The input shift register is 24 bits wide. When PEC is enabled, the input shift register is 32 bits wide, with the last eight bits corresponding to the PEC code (see the Packet Error Checking section for more information about PEC). When writing to a data register, the format shown in Table 10 must be used. When writing to a DAC data register, Bit D15 to Bit D4 are the DAC data bits.
Data Sheet AD5737 Gain Register DREG[2:0] bits to 100 (see Table 15). To write the same offset code to all four DAC channels at the same time, set the DREG[2:0] bits to 101. The offset register coding is straight binary, as shown in Table 16. The default code in the offset register is 0x8000, which results in zero offset programmed to the output (for more information, see the Digital Offset and Gain Control section).
AD5737 Data Sheet CONTROL REGISTERS Main Control Register When writing to a control register, the format shown in Table 18 must be used. See Table 11 for information about the configuration of Bit D23 to Bit D16. The control registers are addressed by setting the DREG[2:0] bits (Bits[D20:D18] in the input shift register) to 111 and then setting the CREG[2:0] bits to select the specific control register (see Table 19). The main control register options are shown in Table 20 and Table 21.
Data Sheet AD5737 DAC Control Register The DAC control register is used to configure each DAC channel. The DAC control register options are shown in Table 22 and Table 23. Table 22. Programming the DAC Control Register D15 0 1 D14 1 D13 0 D12 X1 D11 X1 D10 X1 D9 X1 D8 D7 D6 INT_ENABLE CLR_EN OUTEN D5 RSET D4 DC_DC D3 X1 D2 R2 D1 R1 D0 R0 X = don’t care. Table 23.
AD5737 Data Sheet Software Register The software register allows the user to perform a software reset of the part. This register is also used to set the user toggle bit, D11, in the status register and as part of the watchdog timer feature when that feature is enabled. Bit D12 in the software register can be used to ensure that communication has not been lost between the MCU and the AD5737 and that the datapath lines are working properly (that is, SDIN, SCLK, and SYNC).
Data Sheet AD5737 Slew Rate Control Register This register is used to program the slew rate control for the selected DAC channel. The slew rate control is enabled/disabled and programmed on a per-channel basis. See Table 28 and the Digital Slew Rate Control section for more information. (see Figure 4). This second SPI transfer should be either a request to read another register on a third data transfer or a no operation command.
AD5737 Data Sheet Status Register read back on the SDO pin during every write sequence. Alternatively, if the STATREAD bit is not set, the status register can be read using the normal readback operation (see the Readback Operation section). The status register is a read-only register. This register contains any fault information, as a well as a ramp active bit (Bit D9) and a user toggle bit (Bit D11).
Data Sheet AD5737 DEVICE FEATURES FAULT OUTPUT When data is written to the gain (M) or offset (C) register, the output is not automatically updated. Instead, the next write to the DAC channel uses the new gain and offset values to perform a new calibration and automatically updates the channel. The AD5737 is equipped with a FAULT pin, an active low, open-drain output that allows several AD5737 devices to be connected together to one pull-up resistor for global fault detection.
AD5737 Data Sheet PACKET ERROR CHECKING WATCHDOG TIMER To verify that data has been received correctly in noisy environments, the AD5737 offers the option of packet error checking based on an 8-bit cyclic redundancy check (CRC-8). The device controlling the AD5737 should generate an 8-bit frame check sequence using the following polynomial: When enabled, an on-chip watchdog timer generates an alert signal if 0x195 is not written to the software register within the programmed timeout period.
Data Sheet AD5737 HART CONNECTIVITY Table 34. Slew Rate Update Clock Options The AD5737 has four CHART pins, one corresponding to each output channel. A HART signal can be coupled into these pins. The HART signal appears on the corresponding current output, if the output is enabled. Table 33 shows the recommended input voltages for the HART signal at the CHART pin. If these voltages are used, the current output should meet the HART amplitude specifications.
AD5737 Data Sheet When the slew rate control feature is enabled, all output changes occur at the programmed slew rate (see the DC-to-DC Converter Settling Time section for more information). For example, if the CLEAR pin is asserted, the output slews to the clear value at the programmed slew rate (assuming that the channel is enabled to be cleared). If more than one channel is enabled for digital slew rate control, care must be taken when asserting the CLEAR pin.
Data Sheet AD5737 DC-to-DC Converter On-Board Switch The AD5737 contains a 0.425 Ω internal switch. The switch current is monitored on a pulse-by-pulse basis and is limited to 0.8 A peak current. DC-to-DC Converter Input and Output Capacitor Selection DC-to-DC Converter Inductor Selection The output capacitor affects the ripple voltage of the dc-to-dc converter and indirectly limits the maximum slew rate at which the channel output current can rise.
AD5737 Data Sheet AICC SUPPLY REQUIREMENTS—SLEWING Adding an External Compensation Resistor The AICC current requirement while slewing is greater than in static operation because the output power increases to charge the output capacitance of the dc-to-dc converter. This transient current can be quite large (see Figure 57), although the methods described in the Reducing AICC Current Requirements section can reduce the requirements on the AVCC supply.
Data Sheet AD5737 Using Slew Rate Control EXTERNAL PMOS MODE Using slew rate control can greatly reduce the current requirements of the AVCC supply, as shown in Figure 60. The AD5737 can also be used with an external PMOS transistor per channel, as shown in Figure 61. This mode can be used to limit the on-chip power dissipation of the AD5737, although this mode does not reduce the power dissipation of the total system.
AD5737 Data Sheet APPLICATIONS INFORMATION CURRENT OUTPUT MODE WITH INTERNAL RSET When using the internal RSET resistor, the current output is significantly affected by how many other channels using the internal RSET are enabled and by the dc crosstalk from these channels. The internal RSET specifications in Table 1 are for all four channels enabled with the internal RSET selected and outputting the same code. For every channel enabled with the internal RSET, the offset error decreases.
Data Sheet AD5737 TRANSIENT VOLTAGE PROTECTION AD5737-to-ADSP-BF527 Interface The AD5737 contains ESD protection diodes that prevent damage from normal handling. The industrial control environment can, however, subject I/O circuits to much higher transients. To protect the AD5737 from excessively high voltage transients, external power diodes and a surge current limiting resistor (RP) are required, as shown in Figure 62. A typical value for RP is 10 Ω.
AD5737 Data Sheet Traces GALVANICALLY ISOLATED INTERFACE The power supply lines of the AD5737 should use as large a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. Fast switching signals such as clocks should be shielded with digital ground to prevent radiating noise to other parts of the board and should never be run near the reference inputs.
Data Sheet AD5737 INDUSTRIAL HART CAPABLE ANALOG OUTPUT APPLICATION For transient overvoltage protection, a 24 V transient voltage suppressor (TVS) is placed on the IOUT/VOUT connection. For added protection, clamping diodes are connected from the IOUT_x/VOUT_x pin to the AVDD and GND power supply pins. A 5 kΩ current limiting resistor is also placed in series with the +VSENSE_x input. This is to limit the current to an acceptable level during a transient event.
AD5737 Data Sheet OUTLINE DIMENSIONS 9.10 9.00 SQ 8.90 0.60 MAX 0.60 MAX 64 49 1 PIN 1 INDICATOR 48 PIN 1 INDICATOR 8.85 8.75 SQ 8.65 0.50 BSC 0.50 0.40 0.30 33 32 0.05 MAX 0.02 NOM 0.30 0.23 0.18 0.25 MIN FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. 0.20 REF COMPLIANT TO JEDEC STANDARDS MO-220-VMMD-4 06-13-2012-C SEATING PLANE 16 7.50 REF 0.80 MAX 0.65 TYP 12° MAX 17 BOTTOM VIEW TOP VIEW 1.00 0.85 0.
