Datasheet
AD5737 Data Sheet
Rev. C | Page 28 of 44
CONTROL REGISTERS
When writing to a control register, the format shown in Table 18
must be used. See Table 11 for information about the configura-
tion of Bit D23 to Bit D16. The control registers are addressed
by setting the DREG[2:0] bits (Bits[D20:D18] in the input shift
register) to 111 and then setting the CREG[2:0] bits to select the
specific control register (see Table 19).
Main Control Register
The main control register options are shown in Table 20 and
Table 21. See the Device Features section for more information
about the features controlled by the main control register.
Table 18. Input Shift Register for a Write Operation to a Control Register
MSB
LSB
D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 to D0
R/
W
DUT_AD1 DUT_AD0 1 1 1 DAC_AD1 DAC_AD0 CREG2 CREG1 CREG0 Data
Table 19. Control Register Addresses (CREG[2:0] Bits)
CREG2 (D15) CREG1 (D14) CREG0 (D13) Control Register
0
0
0
Slew rate control register (one per channel)
0 0 1 Main control register
0 1 0 DAC control register (one per channel)
0 1 1 DC-to-DC control register
1 0 0 Software register
Table 20. Programming the Main Control Register
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 to D0
0 0 1 0 STATREAD EWD WD1 WD0 X
1
X
1
OUTEN_ALL DCDC_ALL X
1
1
X = don’t care.
Table 21. Main Control Register Bit Descriptions
Bit Name Description
STATREAD Enable status readback during a write. See the Status Readback During a Write section.
0 = disable status readback (default).
1 = enable status readback.
EWD Enable the watchdog timer. See the Watchdog Timer section.
0 = disable the watchdog timer (default).
1 = enable the watchdog timer.
WD1, WD0 Timeout select bits. Used to select the timeout period for the watchdog timer.
WD1 WD0 Timeout Period (ms)
0 0 5
0 1 10
1 0 100
1 1 200
OUTEN_ALL Setting this bit to 1 enables the output on all four DACs simultaneously. Do not use the OUTEN_ALL bit when using the
OUTEN bit in the DAC control register.
DCDC_ALL Setting this bit to 1 powers up the dc-to-dc converter on all four channels simultaneously. To power down the dc-to-dc
converters, all channel outputs must first be disabled. Do not use the DCDC_ALL bit when using the DC_DC bit in the
DAC control register.