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Industrial I/V Output Driver, Single-Supply,

55 V Maximum Supply, Programmable Ranges

Data Sheet

AD5751

Rev. B Document Feedback

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FEATURES

Current output ranges: 0 mA to 20 mA, 0 mA to 24 mA,

or 4 mA to 20 mA

±0.03% FSR typical total unadjusted error (TUE)

±5 ppm/°C typical output drift

2% overrange

Voltage output ranges: 0 V to 5 V, 0 V to 10 V, 0 V to 40 V

±0.02% FSR typical total unadjusted error (TUE)

±3 ppm/°C typical output drift

Overrange capability on all ranges

Flexible serial digital interface

On-chip output fault detection

PEC error checking

Asynchronous CLEAR function

Power supply range

: 12 V (± 10%) to 55 V (maximum)

Output loop compliance to AV

− 2.75 V

Temperature range: −40°C to +105°C

32-lead 5 mm × 5 mm LFCSP package

APPLICATIONS

Process control

Actuator control

PLCs

GENERAL DESCRIPTION

The AD5751 is a single-channel, low cost, precision, voltage/

current output driver with hardware or software programmable

output ranges. The software ranges are configured via an SPI-/

MICROWIRE™-compatible serial interface. The AD5751 targets

applications in PLC and industrial process control. The analog

input to the AD5751 is provided from a low voltage, single-supply

digital-to-analog converter (DAC) and is internally conditioned

to provide the desired output current/voltage range.

The output current range is programmable across three current

ranges: 0 mA to 20 mA, 0 mA to 24 mA, or 4 mA to 20 mA.

Voltage output is provided from a separate pin that can be

configured to provide 0 V to 5 V, 0 V to 10 V, and 0 V to 40 V

output ranges. An overrange is available on the voltage ranges.

Analog outputs are short-circuit and open-circuit protected and

can drive capacitive loads of 1 µF and inductive loads of 0.1 H.

The device is specified to operate with a power supply range from

10.8 V to 55 V. Output loop compliance is 0 V to AV

− 2.75 V.

The flexible serial interface is SPI and MICROWIRE compatible

and can be operated in 3-wire mode to minimize the digital

isolation required in isolated applications. The interface also

features an optional PEC error checking feature using CRC-8

error checking, useful in industrial environments where data

communication corruption can occur.

The device also includes a power-on reset function ensuring

that the device powers up in a known state (0 V or tristate)

and an asynchronous CLEAR pin that sets the outputs to zero-

scale/midscale voltage output or the low end of the selected

current range.

An HW SELECT pin is used to configure the part for hardware

or software mode on power-up.

Table 1. Related Device

Part Number

Description

AD5422 Single-channel, 16-bit, serial input current

source and voltage output DAC

Summary of content (32 pages)

PAGE 1
Industrial I/V Output Driver, Single-Supply, 55 V Maximum Supply, Programmable Ranges AD5751 Data Sheet FEATURES GENERAL DESCRIPTION Current output ranges: 0 mA to 20 mA, 0 mA to 24 mA, or 4 mA to 20 mA ±0.03% FSR typical total unadjusted error (TUE) ±5 ppm/°C typical output drift 2% overrange Voltage output ranges: 0 V to 5 V, 0 V to 10 V, 0 V to 40 V ±0.
PAGE 2
AD5751 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 OUTEN........................................................................................ 24 Applications ....................................................................................... 1 Software Control ........................................................................ 24 General Description ...................................................
PAGE 3
Data Sheet AD5751 FUNCTIONAL BLOCK DIAGRAM DVCC GND AVDD GND COMP1 COMP2 CLEAR CLRSEL SCLK/OUTEN* SDIN/R0* SYNC/RSET* SDO/VFAULT* HW SELECT VSENSE+ INPUT SHIFT REGISTER AND CONTROL LOGIC VOUT RANGE SCALING VOUT VOUT SHORT FAULT STATUS REGISTER AVDD VIN R3 R2 VREF RESET IOUT RANGE SCALING IOUT OVERTEMP NC/IFAULT* REXT1 VOUT SHORT FAULT RSET REXT2 IOUT OPEN FAULT POWERON RESET AD5751 AD2/R1* AD1/R2* IOUT OPEN FAULT AD0/R3* *DENOTES SHARED PIN.
PAGE 4
AD5751 Data Sheet SPECIFICATIONS AVDD = 12 V (± 10%) to 55 V (maximum), DVCC = 2.7 V to 5.5 V, GND = 0 V. IOUT: RLOAD = 300 Ω. All specifications TMIN to TMAX, unless otherwise noted. Table 2. Parameter 1 INPUT VOLTAGE RANGE Min Input Leakage Current REFERENCE INPUT Reference Input Voltage −1 Input Leakage Current VOLTAGE OUTPUT Output Voltage Ranges −1 +1 μA 0 0 5 10 V V 0 0 40 6 V V 0 0 12 44 V V +0.1 +0.05 +0.3 +0.1 +0.02 +14 +5 +4 +3 +2.2 +20 +17 +0.05 +0.04 +0.09 +0.
PAGE 5
Data Sheet Parameter 1 Capacitive Load Stability RLOAD = ∞ RLOAD = 1 kΩ RLOAD = ∞ 0F AD5751 Min Typ Max Unit 1 1 2 nF nF μF DC Output Impedance Settling Time 0 V to 5 V Range, ¼ to ¾ Step 0 V to 5 V Range, 40 mV Input Step 0 V to 40 V Range, ¼ to ¾ Step Slew Rate Output Noise 0.12 Ω 7 4.5 15.8 2 3.5 45.
PAGE 6
AD5751 Parameter 1 Gain TC4 Full-Scale Error Full-Scale TC4 OUTPUT CHARACTERISTICS4 Current Loop Compliance Voltage Resistive Load Data Sheet Min −0.1 −0.07 VOH, Output High Voltage SDO VOL, Output Low Voltage VOH, Output High Voltage High Impedance Output Capacitance High Impedance Leakage Current POWER REQUIREMENTS AVDD DVCC Input Voltage AIDD DICC Power Dissipation Max +0.1 +0.07 ±0.
PAGE 7
Data Sheet AD5751 TIMING CHARACTERISTICS AVDD = 12 V (± 10%) to 55 V (maximum), DVCC = 2.7 V to 5.5 V, GND = 0 V. VOUT: RLOAD = 2 kΩ (5 kΩ for 0 V to 40 V range), CL = 200 pF, IOUT: RLOAD = 300 Ω. All specifications TMIN to TMAX, unless otherwise noted. Table 3. Parameter1, 2 t1 t2 t3 t4 t5 t6 t7 t8 t9, t10 t11 t12 t13 1 2 Limit at TMIN, TMAX 20 8 8 5 10 5 5 5 1.
PAGE 8
AD5751 Data Sheet SCLK SYNC SDIN t11 A2 A1 A0 R=1 0 X X X X X X X X X X X SDO X X X X X R3 R2 R1 R0 CLRSEL OUTEN Figure 3. Readback Mode Timing Diagram Rev.
PAGE 9
Data Sheet AD5751 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Transient currents of up to 100 mA do not cause SCR latch-up. Table 4. Parameter AVDD to GND DVCC to GND Digital Inputs to GND Digital Outputs to GND VREF to GND VSENSE+ to GND VIN to GND VOUT, IOUT to GND Operating Temperature Range Industrial Storage Temperature Range Junction Temperature (TJ max) 32-Lead LFCSP Package θJA Thermal Impedance 1 Lead Temperature Soldering 1 Rating −0.3 V to +58 V −0.3 V to +7 V −0.
PAGE 10
AD5751 Data Sheet 32 31 30 29 28 27 26 25 NC/IFAULT FAULT/TEMP RESET HW SELECT NC NC NC NC PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 2 3 4 5 6 7 8 PIN 1 INDICATOR AD5751 TOP VIEW (Not to Scale) 24 23 22 21 20 19 18 17 VSENSE+ VOUT GND GND COMP1 COMP2 IOUT AVDD NOTES 1. NC = NO CONNECT. 2. THE EXPOSED PADDLE IS TIED TO GND. 07269-005 AD2/R1 AD1/R2 AD0/R3 REXT2 REXT1 VREF VIN GND 9 10 11 12 13 14 15 16 SDO/VFAULT CLRSEL CLEAR DVCC GND SYNC/RSET SCLK/OUTEN SDIN/R0 Figure 4.
PAGE 11
Data Sheet Pin No. 10 Mnemonic AD1/R2 11 AD0/R3 12, 13 REXT2, REXT1 14 15 16 17 18 19, 20 VREF VIN GND AVDD IOUT COMP2, COMP1 21 22 23 24 25, 26, 27, 28 29 GND GND VOUT VSENSE+ NC HW SELECT 30 RESET 31 FAULT/TEMP 32 NC/IFAULT 33 (EPAD) Exposed paddle AD5751 Description Device Addressing Bit (AD1). In software mode, this pin, in conjunction with AD0 and AD2, allows up to eight devices to be addressed on one bus. Range Decode Bit (R2).
PAGE 12
AD5751 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS 0.10 0.006 0.004 0.002 0 –0.002 –0.004 –0.006 4.096 VIN (V) 0.06 0.04 0 –0.02 –0.04 –0.06 –0.08 –0.10 –40 105 0.05 0.010 0V TO 5V RANGE 0V TO 10V RANGE 0V TO 40V RANGE 0.008 0V TO 5V RANGE 0V TO 10V RANGE 0V TO 40V RANGE 0.04 FULL-SCALE ERROR (%FSR) 0.006 0.004 0.002 0 –0.002 –0.004 0.03 0.02 0.01 0 –0.01 –0.02 –0.006 –0.03 –0.04 105 25 TEMPERATURE (°C) –40 07269-015 –0.010 –40 Figure 6. Integral Nonlinearity Error vs.
PAGE 13
Data Sheet AD5751 1.00 4.0 0V TO 5V RANGE 0V TO 10V RANGE 0V TO 40V RANGE 3.5 0.95 2.5 HEADROOM (V) OFFSET ERROR (mV) 3.0 VDD HEADROOM, LOAD OFF 2.0 1.5 1.0 0.5 0.90 0.85 0.80 0 –0.5 0.75 –1.0 25 TEMPERATURE (°C) 105 0.70 –40 0.007 5V LINEARITY, NO LOAD 10V LINEARITY, NO LOAD 40V LINEARITY, NO LOAD 5V RANGE 0.006 OUTPUT VOLTAGE DELTA (V) 0.006 0.004 0.002 0 –0.002 –0.004 –0.006 0.005 0.004 0.003 0.002 0.001 0 –0.010 24 48 SUPPLY VOLTAGE (V) 55 –0.
PAGE 14
AD5751 Data Sheet 12 10 VOLTAGE (V) 8 6 2 –3 2 7 12 17 22 1s/DIV 07269-026 5µV/DIV 0 –8 07269-029 4 27 TIME (µs) Figure 17. Full-Scale Negative Step, 10 V Range Figure 20. Peak-to-Peak Noise (0.1 Hz to 10 Hz Bandwidth) 40 35 30 20 15 10 0 100µV/DIV –0.5 0 0.5 1.0 1.5 2.0 2.5 TIME (ms) 1s/DIV 07269-027 –5 –1.0 07269-030 5 Figure 18. VOUT vs. Time on Power-Up, Load = 2 kΩ || 200 pF Figure 21. Peak-to-Peak Noise (100 kHz Bandwidth) 4.0 1.0 3.5 0.8 3.0 1 VDD 0.6 2.
PAGE 15
Data Sheet AD5751 CURRENT OUTPUT 0.003 0.002 0.001 0 –0.001 –0.002 –0.003 0 –0.002 –0.004 –0.006 4.096 55V 0.05 –0.02 4.096 3.511 3.803 3.218 2.926 2.633 VIN (V) 07269-036 VIN (V) 07269-033 4.096 3.803 3.511 3.218 2.926 2.633 2.341 2.048 1.755 1.463 1.170 0.878 0.585 –0.05 Figure 27. Total Unadjusted Error vs. VIN, External RSET Resistor Figure 24. Integral Nonlinearity Error vs. VIN, Internal RSET Resistor 0.
PAGE 16
AD5751 Data Sheet 0.005 4mA TO 20mA EXTERNAL RSET POSITIVE TUE 0mA TO 20mA EXTERNAL RSET POSITIVE TUE 0mA TO 24mA EXTERNAL RSET POSITIVE TUE 0.004 INTEGRAL NONLINEARITY (%FSR) 0.010 0.005 0 –0.005 –0.010 4mA TO 20mA EXTERNAL RSET NEGATIVE TUE 0mA TO 20mA EXTERNAL RSET NEGATIVE TUE 0mA TO 24mA EXTERNAL RSET NEGATIVE TUE 24V 48V SUPPLY VOLTAGE (AVDD) 55V –0.003 0.10 POSITIVE/NEGATIVE TUE (%FSR) 0mA TO 24mA INTERNAL RSET NEGATIVE TUE 4mA TO 20mA INTERNAL RSET POSITIVE TUE –0.005 –0.010 –0.
PAGE 17
Data Sheet AD5751 50 4 45 3 30 25 20 15 4mA TO 20mA EXTERNAL RSET 0mA TO 20mA EXTERNAL RSET 0mA TO 24mA EXTERNAL RSET 0 –40 25 TEMPERATURE (°C) 105 –1 4mA TO 20mA EXTERNAL RSET 0mA TO 20mA EXTERNAL RSET 0mA TO 24mA EXTERNAL RSET –2 –3 Figure 35. Zero-Scale Error vs. Temperature, External RSET Sense Resistor –40 0.05 35 0.
PAGE 18
AD5751 Data Sheet 0.10 0.08 0.000010 12 4mA TO 20mA EXTERNAL RSET 0mA TO 20mA EXTERNAL RSET 0mA TO 24mA EXTERNAL RSET 0.000008 10 0.000006 8 0.02 0 0.000004 0.000002 6 IOUT 0 4 –0.02 –0.04 IOUT (A) 0.04 VDD (V) GAIN ERROR (%FSR) 0.06 –0.000002 –0.000004 2 –0.000006 –0.06 0 VDD –40 25 TEMPERATURE (°C) 105 –2 –10 –0.000010 –8 –6 –4 –2 0 2 4 8 6 10 TIME (ms) Figure 41. Gain Error vs. Temperature, External RSET Sense Resistor Figure 44. Output Current vs.
PAGE 19
Data Sheet AD5751 3000 4.10 2500 4.05 4.00 DVCC = 5V AIDD (mA) DICC (µA) 2000 1500 3.95 3.90 1000 3.85 500 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 LOGIC LEVEL (V) 5.0 3.75 07269-056 0 24 Figure 47. DICC vs. Logic Input Voltage Figure 49. AIDD vs. AVDD, IOUT = 0 mA 4.10 4.05 3.95 3.90 3.85 3.80 3.75 48 AVDD (V) 55 07269-057 AIDD (mA) 4.00 24 48 AVDD (V) Figure 48. AIDD vs. AVDD, VOUT = 0 V Rev. B | Page 19 of 32 55 07269-058 3.
PAGE 20
AD5751 Data Sheet TERMINOLOGY Zero-Scale TC Zero-scale TC is a measure of the change in zero-scale error with a change in temperature. Zero-scale error TC is expressed in ppm FSR/°C. Total Unadjusted Error (TUE) TUE is a measure of the output error taking all the various errors into account: INL error, offset error, gain error, and output drift over supplies, temperature, and time. TUE is expressed as a percentage of full-scale range (% FSR).
PAGE 21
Data Sheet AD5751 THEORY OF OPERATION one time. The output range is selected by programming the R3 to R0 bits in the control register (see Table 7 and Table 8). The AD5751 is a single-channel, low cost, precision, voltage/ current output driver with hardware or software programmable output ranges. The software ranges are configured via an SPI-/ MICROWIRE-compatible serial interface. The hardware ranges are programmed using the range pins (R0 to R3).
PAGE 22
AD5751 Data Sheet AVDD AGND ADP1720 AVDD GND AD5751 ADR392 SCLK VDD REFIN VOUT RANGE SCALE SDI/DIN MCU SDO VSENSE+ VREF VOUT 0V TO 5V, 0V TO 10V, 0V TO 40V VIN AD506x AD566x SYNC1 IOUT RANGE SCALE DVCC IOUT 0mA TO 20mA, 0mA TO 24mA, 4mA TO 20mA HW SELECT OUTEN R3 R2 R1 VFAULT IFAULT R0 07269-007 TEMP OUTPUT RANGE SELECT PINS Figure 51. Typical System Configuration in Hardware Mode Using Internal DAC Reference (Pull-Up Resistors Not Shown for Open-Drain Outputs) Table 6.
PAGE 23
Data Sheet AD5751 CURRRENT OUTPUT ARCHITECTURE Driving Large Capacitive Loads The voltage input from the analog input VIN core (0 V to 4.096 V) is either converted to a current (see Figure 52), which is then mirrored to the supply rail so that the application simply sees a current source output with respect to an internal reference voltage, or it is buffered and scaled to output a software-selectable unipolar voltage range (see Figure 53).
PAGE 24
AD5751 Data Sheet DEFAULT REGISTERS AT POWER-ON disabled, both the current and voltage channels go into tristate. The user must set the OUTEN bit to enable the output and simultaneously set the output range configuration. The AD5751 power-on-reset circuit ensures that all registers are loaded with zero code. In hardware mode, the output can be enabled or disabled using the OUTEN pin. When the output is disabled, both the current and voltage channels go into tristate.
PAGE 25
Data Sheet Bit R3, R2, R1, R0 CLRSEL OUTEN Clear RSET Reset AD5751 Description Selects the output configuration in conjunction with RSET. RSET R3 R2 R1 R0 Output Configuration 0 0 0 0 0 4 mA to 20 mA (external 15 kΩ current sense resistor). 0 0 0 0 1 0 mA to 20 mA (external 15 kΩ current sense resistor). 0 0 0 1 0 0 mA to 24 mA (external 15 kΩ current sense resistor). 0 0 0 1 1 Unused command. Do not program. 0 0 1 0 0 Unused command. Do not program. 0 0 1 0 1 0 V to 5 V. 0 0 1 1 0 0 V to 10 V.
PAGE 26
AD5751 Data Sheet Readback Operation HARDWARE CONTROL Readback mode is activated by selecting the correct device address (A2, A1, A0) and then setting the R/W bit to 1. By default, the SDO pin is disabled. After having addressed the AD5751 for a read operation, setting R/W to 1 enables the SDO pin and SDO data is clocked out on the 5th rising edge of SCLK. After the data has been clocked out on SDO, a rising edge on SYNC disables (tristate) the SDO pin again.
PAGE 27
Data Sheet AD5751 DETAILED DESCRIPTION OF FEATURES • OUTPUT FAULT ALERT—SOFTWARE MODE In software mode, the AD5751 is equipped with one FAULT pin; this is an open-drain output allowing several AD5751 devices to be connected together to one pull-up resistor for global fault detection.
PAGE 28
AD5751 Data Sheet PROGRAMMABLE OVERRANGE MODES PACKET ERROR CHECKING The AD5751 contains an overrange mode for most of the available ranges. The overranges are selected by configuring the R3, R1, R1, and R0 bits (or pins) accordingly. To verify that data has been received correctly in noisy environments, the AD5751 offers the option of error checking based on an 8-bit (CRC-8) cyclic redundancy check.
PAGE 29
Data Sheet AD5751 APPLICATIONS INFORMATION TRANSIENT VOLTAGE PROTECTION THERMAL CONSIDERATIONS The AD5751 contains ESD protection diodes that prevent damage from normal handling. The industrial control environment can, however, subject I/O circuits to much higher transients. To protect the AD5751 from excessively high voltage transients, external power diodes and a surge current limiting resistor may be required, as shown in Figure 55.
PAGE 30
AD5751 Data Sheet In any circuit where accuracy is important, careful consideration of the power supply and ground return layout helps to ensure the rated performance. The PCB on which the AD5751 is mounted should be designed so that the AD5751 lies on the analog plane. The AD5751 should have ample supply bypassing of 10 μF in parallel with 0.1 μF on each supply, located as close to the package as possible, ideally right up against the device. The 10 μF capacitors are the tantalum bead type. The 0.
PAGE 31
Data Sheet AD5751 OUTLINE DIMENSIONS 5.10 5.00 SQ 4.90 0.60 MAX 0.60 MAX 25 32 24 0.50 BSC 3.25 3.10 SQ 2.95 EXPOSED PAD 17 TOP VIEW 1.00 0.85 0.80 SEATING PLANE 12° MAX 0.80 MAX 0.65 TYP 0.30 0.25 0.18 0.50 0.40 0.30 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF PIN 1 INDICATOR 8 16 9 BOTTOM VIEW 0.25 MIN 3.50 REF FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET.