Datasheet
Table Of Contents
- Features
- Applications
- General Description
- Revision History
- Functional Block Diagram
- Specifications
- Absolute Maximum Ratings
- Pin Configuration and Function Descriptions
- Typical Performance Characteristics
- Terminology
- Theory of Operation
- Registers
- Design Features
- Applications Information
- Layout Guidelines
- Outline Dimensions

AD5764R Data Sheet
Rev. D | Page 2 of 32
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Functional Block Diagram .............................................................. 3
Specifications ..................................................................................... 4
AC Performance Characteristics ................................................ 6
Timing Characteristics ................................................................ 7
Absolute Maximum Ratings .......................................................... 10
Thermal Resistance .................................................................... 10
ESD Caution ................................................................................ 10
Pin Configuration and Function Descriptions ........................... 11
Typical Performance Characteristics ........................................... 13
Terminology .................................................................................... 19
Theory of Operation ...................................................................... 21
DAC Architecture ....................................................................... 21
Reference Buffers ........................................................................ 21
Serial Interface ............................................................................ 21
Simultaneous Updating via
LDAC
........................................... 22
Transfer Function ....................................................................... 23
Asynchronous Clear (
CLR
) ....................................................... 23
Registers ........................................................................................... 24
Function Register ....................................................................... 24
Data Register ............................................................................... 25
Coarse Gain Register ................................................................. 25
Fine Gain Register ...................................................................... 25
Offset Register ............................................................................ 26
Offset and Gain Adjustment Worked Example ...................... 26
Design Features ............................................................................... 27
Analog Output Control ............................................................. 27
Digital Offset and Gain Control ............................................... 27
Programmable Short-Circuit Protection ................................ 27
Digital I/O Port ........................................................................... 27
Die Temperature Sensor ............................................................ 27
Local Ground Offset Adjust ...................................................... 27
Applications Information .............................................................. 28
Typical Operating Circuit ......................................................... 28
Layout Guidelines ........................................................................... 30
Galvanically Isolated Interface ................................................. 30
Microprocessor Interfacing ....................................................... 30
Evaluation Board ........................................................................ 31
Outline Dimensions ....................................................................... 32
Ordering Guide .......................................................................... 32
REVISION HISTORY
10/11—Rev. C to Rev. D
Changed 50 MHz to 30 MHz ....................................... Throughout
Changes to t
1
, t
2
, and t
3
Parameters, Table 3 .................................. 7
7/11—Rev. B to Rev. C
Changed 30 MHz to 50 MHz Throughout.................................... 1
Changes to t
1
, t
2
, and t
3
Parameters, Table 3 .................................. 7
8/09—Rev. A to Rev. B
Deleted Endnote 1 in Table 1 .......................................................... 4
Deleted Endnote 1 in Table 2 .......................................................... 6
Deleted Endnote 1 and Changes t
6
Parameter in Tabl e 3 ............ 7
Changes to Ordering Guide .......................................................... 32
2/09—Rev. 0 to Rev. A
Changes to Table 1 Test Conditions/Comments and
Added Endnote to Table 1 ................................................................ 4
Added Endnote to Table 2 ................................................................ 6
Added Endnote to Table 3 ................................................................ 7
10/08—Revision 0: Initial Version