Datasheet

Data Sheet AD5764R
Rev. D | Page 7 of 32
TIMING CHARACTERISTICS
AV
DD
= 11.4 V to 16.5 V, AV
SS
= −11.4 V to −16.5 V, AGND = DGND = REFGND = PGND = 0 V; REFAB = REFCD = 5 V external;
DV
CC
= 2.7 V to 5.25 V, R
LOAD
= 10 kΩ, C
L
= 200 pF. All specifications T
MIN
to T
MAX
, unless otherwise noted.
Table 3.
Parameter
1, 2, 3
Limit at T
MIN
, T
MAX
Unit Description
t
1
33 ns min SCLK cycle time
t
2
13 ns min SCLK high time
t
3
13 ns min SCLK low time
t
4
13 ns min
SYNC falling edge to SCLK falling edge setup time
t
5
4
13 ns min
24
th
SCLK falling edge to SYNC rising edge
t
6
90 ns min
Minimum
SYNC high time
t
7
2 ns min Data setup time
t
8
5 ns min Data hold time
t
9
1.7 µs min
SYNC rising edge to LDAC falling edge (all DACs updated)
480 ns min
SYNC rising edge to LDAC falling edge (single DAC updated)
t
10
10
ns min
LDAC pulse width low
t
11
500 ns max
LDAC falling edge to DAC output response time
t
12
10 µs max DAC output settling time
t
13
10 ns min
CLR pulse width low
t
14
2 µs max
CLR pulse activation time
t
15
5, 6
25 ns max SCLK rising edge to SDO valid
t
16
13 ns min
SYNC rising edge to SCLK falling edge
t
17
2 µs max
SYNC rising edge to DAC output response time (LDAC = 0)
t
18
170 ns min
LDAC falling edge to SYNC rising edge
1
Guaranteed by design and characterization; not production tested.
2
All input signals are specified with t
R
= t
F
= 5 ns (10% to 90% of DV
CC
) and timed from a voltage level of 1.2 V.
3
See Figure 2, Figure 3, and Figure 4.
4
Standalone mode only.
5
Measured with the load circuit of Figure 5.
6
Daisy-chain mode only.