Datasheet

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System Ready, 20-Bit, ±2LSB INL,

Voltage Output DAC

Data Sheet

AD5790

Rev. D Document Feedback

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FEATURES

Single 20-bit voltage output DAC, ±2 LSB INL

8 nV/√Hz output noise spectral density

0.1 LSB long-term linearity error stability

±0.018 ppm/°C gain error temperature coefficient

2.5 µs output voltage settling time

3.5 nV-sec midscale glitch impulse

Integrated precision reference buffers

Operating temperature range: −40°C to +125°C

4 mm × 5 mm LFCSP package

Wide power supply range of up to ±16.5 V

35 MHz Schmitt-triggered digital interface

1.8 V compatible digital interface

APPLICATIONS

Medical instrumentation

Test and measurement

Industrial control

Scientific and aerospace instrumentation

Data acquisition systems

Digital gain and offset adjustment

Power supply control

FUNCTIONAL BLOCK DIAGRAM

6.8kΩ

6kΩ

6.8kΩ

R1 R

DAC

REG

2020

INPUT

SHIFT

AND

CONTRO

LOGIC

POWER-ON-RESET

AND CLEAR LOGIC

AD5790

IOV

SDIN

REFP

AGNDV

DGND

SCLK

SYNC

SDO

LDAC

CLR

RESET

INV

OUT

20-BIT

DAC

REFN

10239-001

Figure 1.

Table 1. Related Devices

Part No. Description

AD5791 20-bit, 1 LSB accurate DAC

AD5780 18-bit, ±1 LSB INL, voltage output DAC ,

buffered reference inputs

AD5781 18-bit, ±1 LSB INL, voltage Output DAC ,

unbuffered reference inputs

AD5760

16-bit, ±0.5 LSB INL, voltage Output DAC

AD5541A/AD5542A 16-bit, 1 LSB accurate 5 V DAC

GENERAL DESCRIPTION

The AD5790

is a single 20-bit, unbuffered voltage-output DAC

that operates from a bipolar supply of up to 33 V. The AD5790

accepts a positive reference input in the range of 5 V to V

−

2.5 V and a negative reference input in the range of V

+ 2.5 V

to 0 V. T h e AD5790 offers a relative accuracy specification of

±2 LSB maximum range, and operation is guaranteed mono-

tonic with a −1 LSB to +3 LSB DNL specification.

The part uses a versatile 3-wire serial interface that operates at

clock rates of up to 35 MHz and is compatible with standard

SPI, QSPI™, MICROWIRE™, and DSP interface standards.

Reference buffers are also provided on chip. The part incorpo-

rates a power-on reset circuit that ensures the DAC output

powers up to 0 V in a known output impedance state and

remains in this state until a valid write to the device takes place.

The part provides a disable feature that places the output in a

defined load state. The part provides an output clamp feature

that places the output in a defined load state.

Protected by U.S. Patent No. 7,884,747 and 8,089,380.

PRODUCT HIGHLIGHTS

1. 20-bit resolution.

2. Wide power supply range of up to ±16.5 V.

3. −40°C to +125°C operating temperature range.

4. Low 8 nV/√Hz noise.

5. Low ±0.018 ppm/°C gain error temperature coefficient.

COMPANION PRODUCTS

Output Amplifier Buffer: AD8675, ADA4898-1, ADA4004-1

External Reference: ADR445, ADR4550

DC-to-DC Design Tool: ADIsimPower™

Additional companion products on the AD5790 product page

Summary of content (28 pages)

PAGE 1
System Ready, 20-Bit, ±2LSB INL, Voltage Output DAC AD5790 Data Sheet FEATURES FUNCTIONAL BLOCK DIAGRAM VCC VDD VREFP A1 IOVCC 6.8kΩ 6.8kΩ R1 RFB RFB INV SDIN INPUT SHIFT REGISTER AND CONTROL LOGIC SCLK SYNC SDO 20 DAC REG 20 20-BIT DAC VOUT 6kΩ LDAC CLR POWER-ON-RESET AND CLEAR LOGIC RESET DGND VSS AD5790 VREFN AGND 10239-001 Single 20-bit voltage output DAC, ±2 LSB INL 8 nV/√Hz output noise spectral density 0.1 LSB long-term linearity error stability ±0.
PAGE 2
AD5790 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 DAC Architecture....................................................................... 18 Applications ....................................................................................... 1 Serial Interface ............................................................................ 18 Functional Block Diagram ................................................
PAGE 3
Data Sheet AD5790 SPECIFICATIONS VDD = 12.5 V to 16.5 V, VSS = −16.5 V to −12.5 V, VREFP = 10 V, VREFN = −10 V, VCC = 2.7 V to +5.5 V, IOVCC = 1.71 V to 5.5 V, RL = unloaded, CL = unloaded, TMIN to TMAX, unless otherwise noted. Table 2.
PAGE 4
AD5790 Parameter Output Enabled Glitch Impulse Digital Feedthrough DC Output Impedance (Normal Mode) DC Output Impedance (Output Clamped to Ground) REFERENCE INPUTS VREFP Input Range VREFN Input Range Input Bias Current Input Capacitance LOGIC INPUTS Input Current 5 Input Low Voltage, VIL Input High Voltage, VIH Pin Capacitance LOGIC OUTPUT (SDO) Output Low Voltage, VOL Output High Voltage, VOH High Impedance Leakage Current High Impedance Output Capacitance POWER REQUIREMENTS VDD VSS VCC IOVCC IDD ISS ICC
PAGE 5
Data Sheet AD5790 TIMING CHARACTERISTICS VCC = 2.7 V to 5.5 V; all specifications TMIN to TMAX, unless otherwise noted. Table 3. Parameter t1 2 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 1 2 Limit 1 IOVCC = 1.71 V to 3.3 V IOVCC = 3.3 V to 5.
PAGE 6
AD5790 Data Sheet t7 t1 SCLK 1 2 24 t3 t6 t2 t4 t5 SYNC t9 t8 SDIN DB23 DB0 t10 t12 t11 LDAC t13 VOUT t14 VOUT t15 CLR t16 VOUT t21 RESET 10239-002 t22 VOUT Figure 2. Write Mode Timing Diagram t1 t17 SCLK 1 2 24 t3 t6 t20 t7 1 2 24 t2 t5 t4 t5 t17 SYNC SDIN t9 DB23 DB0 INPUT WORD SPECIFIES REGISTER TO BE READ NOP CONDITION t18 t19 DB23 SDO REGISTER CONTENTS CLOCKED OUT Figure 3. Readback Mode Timing Diagram Rev.
PAGE 7
Data Sheet AD5790 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Transient currents of up to 100 mA do not cause SCR latch-up. Table 4.
PAGE 8
AD5790 Data Sheet 24 23 22 21 20 INV DNC DNC DNC RFB PIN CONFIGURATION AND FUNCTION DESCRIPTIONS AD5790 TOP VIEW (Not to Scale) 19 18 17 16 15 14 13 AGND VSS VSS VREFN DGND SYNC SCLK NOTES 1. DNC = DO NOT CONNECT. DO NOT CONNECT TO THIS PIN. 2. NEGATIVE ANALOG SUPPLY CONNECTION (VSS). A VOLTAGE IN THE RANGE OF –16.5 V TO –2.5 V CAN BE CONNECTED. VSS SHOULD BE DECOUPLED TO AGND. THE PADDLE CAN BE LEFT ELECTRICALLY UNCONNECTED PROVIDED THAT A SUPPLY CONNECTION IS MADE AT THE VSS PINS.
PAGE 9
Data Sheet AD5790 TYPICAL PERFORMANCE CHARACTERISTICS AD8675 OUTPUT BUFFER TA = 25°C 1.25 2.0 AD8675 OUTPUT BUFFER TA = 25°C 1.5 0.75 1.0 INL (LSB) INL (LSB) 0.5 0.25 –0.25 0 –0.5 –1.0 –0.75 –1.5 0 200000 400000 600000 800000 DAC CODE 1000000 –3.0 1200000 Figure 5. Integral Nonlinearity Error vs. DAC Code, ±10 V Span 2.5 0 200000 400000 600000 800000 1000000 1200000 DAC CODE Figure 8. Integral Nonlinearity Error vs. DAC Code, 5 V Span, ×2 Gain Mode 2.
PAGE 10
AD5790 3.0 Data Sheet AD8675 OUTPUT BUFFER TA = 25°C 2.5 1.4 DNL ERROR (LSB) 1.0 0.5 0 1.0 0.8 0.6 0.4 VDD = +15V VSS = –15V AD8675 OUTPUT BUFFER 0.2 –0.5 0 400000 600000 800000 1000000 –0.2 –40 10239-012 200000 0 1200000 DAC CODE –20 0 20 40 60 80 100 TEMPERATURE (°C) 10239-015 DNL (LSB) 1.5 Figure 14. Differential Nonlinearity Error vs. Temperature Figure 11. Differential Nonlinearity Error vs. DAC Code, 5 V Span 1.5 2.
PAGE 11
Data Sheet AD5790 1.4 11 TA = 25°C VREFP = 5V 9 VREFN = 0V AD8675 OUTPUT BUFFER DNL MAX ZERO-SCALE ERROR (LSB) DNL ERROR (LSB) 1.0 0.8 0.6 TA = 25°C VREFP = +10V VREFN = –10V AD8675 OUTPUT BUFFER 0.4 0.2 DNL MIN –0.2 12.5 13.0 13.5 14.0 14.5 15.0 5 3 1 –1 –3 15.5 16.0 16.5 VDD/|VSS| (V) –5 7.5 10239-018 0 7 8.5 9.5 11.5 10.5 12.5 Figure 17. Differential Nonlinearity Error vs. Supply Voltage, ±10 V Span 1.2 –0.4 1.0 –0.6 MIDSCALE ERROR (LSB) DNL ERROR (LSB) 15.5 16.
PAGE 12
AD5790 Data Sheet 2.0 6.0 5.8 5.6 1.4 GAIN ERROR (LSB) 1.2 1.0 0.8 0.6 0.4 5.4 5.2 5.0 4.8 4.6 4.4 TA = 25°C V = 5V 4.2 VREFP = 0V REFN AD8675 OUTPUT BUFFER 4.0 7.5 8.5 9.5 10.5 11.5 0 12.5 13.0 13.5 14.0 14.5 15.0 15.5 16.0 16.5 VDD/|VSS| (V) 10239-024 0.2 13.5 14.5 15.5 16.5 Figure 26. Gain Error vs. Supply Voltage, 5 V Span Figure 23. Full-Scale Error vs. Supply Voltage, ±10 V Span 1.25 8 TA = 25°C V = 5V 6 VREFP = 0V REFN AD8675 OUTPUT BUFFER 4 INL MAX 0.75 2 0.
PAGE 13
Data Sheet AD5790 –4.0 –4.5 –0.7 –0.9 –5.0 –5.5 –6.0 –1.1 –6.5 –1.3 –7.0 –1.5 5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0 VREFP /|VREFN | (V) TA = 25°C VDD = +15V VSS = –15V AD8675 OUTPUT BUFFER –7.5 5.0 7.0 7.5 8.5 8.0 9.0 9.5 10.0 Figure 32. Gain Error vs. Reference Voltage 7.0 TA = 25°C VREFP = +15V VREFN = –15V AD8675 OUTPUT BUFFER 6.5 FULL-SCALE ERROR (LSB) MIDSCALE ERROR (LSB) –1.5 6.5 VREFP /|VREFN | (V) Figure 29. Zero-Scale Error vs. Reference Voltage –1.0 6.
PAGE 14
AD5790 Data Sheet 0.010 5 ±10V SPAN +10V SPAN +5V SPAN 0.008 IDD 0.006 1 0.004 –1 IDD/ISS (mA) –3 –5 0.002 0 –0.002 –0.004 –7 –0.006 –9 20 40 80 60 100 TEMPERATURE (°C) –0.010 –20 VDD = +15V VSS = –15V AD8675 OUTPUT BUFFER –6 0 VOUT (V) 2 –8 –4 –12 –6 –14 –8 0 20 40 60 80 100 TEMPERATURE (°C) –10 –1 TA = 25°C 800 700 20 0 1 2 3 4 5 4 5 Figure 39.
PAGE 15
Data Sheet AD5790 6 10 9 5 OUTPUT GLITCH (nV-sec) 8 6 5 4 3 VREFP = +10V VREFN = –10V RC LOW-PASS FILTER UNITY GAIN MODE ADA4898-1 0 –1 0 1 2 3 4 4 3 2 1 5 TIME (µs) 0 CODE Figure 41. 500 Code Step Settling Time Figure 44.
PAGE 16
AD5790 Data Sheet 200 VDD = +15V VSS = –15V VREFP = +10V VREFN = –10V VDD = +15V VSS = –15V VREFP = +10V VREFN = –10V UNITY GAIN ADA4898-1 180 OUTPUT VOLTAGE (mV) 160 10 140 120 100 80 60 40 20 1 10 100 1k FREQUENCY (Hz) 10k Figure 47. Noise Spectral Density vs. Frequency –20 0 1 2 3 4 5 TIME (µs) Figure 48. Glitch Impulse on Removal of Output Clamp Rev. D | Page 16 of 28 6 10239-048 0 1 0.
PAGE 17
Data Sheet AD5790 TERMINOLOGY Relative Accuracy Relative accuracy, or integral nonlinearity (INL), is a measure of the maximum deviation, in LSB, from a straight line passing through the endpoints of the DAC transfer function. A typical INL error vs. code plot is shown in Figure 5. Differential Nonlinearity (DNL) Differential nonlinearity is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes.
PAGE 18
AD5790 Data Sheet THEORY OF OPERATION R R R VOUT 2R 2R ..................... 2R 2R 2R .......... 2R S0 S1 ..................... S13 E62 E61......... E0 VREFP VREFN 14-BIT R-2R LADDER DAC ARCHITECTURE 10239-050 The AD5790 is a high accuracy, fast settling, single, 20-bit, serial input, voltage-output DAC. It operates from a VDD supply voltage of 7 V to 16.5 V and a VSS supply of −16.5 V to -2.5 V. Data is written to the AD5790 in a 24-bit word format via a 3-wire serial interface.
PAGE 19
Data Sheet AD5790 STANDALONE OPERATION Synchronous DAC Update The serial interface works with both a continuous and noncontinuous serial clock. A continuous SCLK source can be used only if SYNC is held low for the correct number of clock cycles. In this mode, LDAC is held low while data is being clocked into the input shift register. The DAC output is updated on the rising edge of SYNC.
PAGE 20
AD5790 Data Sheet Table 8. Hardware Control Pins Truth Table LDAC X1 X1 0 0 1 CLR X1 X1 0 1 0 1 0 1 0 1 0 1 0 1 RESET 0 1 1 1 1 1 1 1 1 1 1 1 Function The AD5790 is in reset mode. The device cannot be programmed. The AD5790 is returned to its power-on state. All registers are set to their default values. The DAC register is loaded with the clearcode register value and the output is set accordingly. The output is set according to the DAC register value.
PAGE 21
Data Sheet AD5790 Control Register is asserted. The output value depends on the DAC coding that is being used, either binary or twos complement. The default register value is 0. The control register controls the mode of operation of the AD5790. Clearcode Register The clearcode register sets the value to which the DAC output is set when the CLR pin or CLR bit in the software control register Table 10.
PAGE 22
AD5790 Data Sheet Software Control Register This is a write only register in which writing a 1 to a particular bit has the same effect as pulsing the corresponding pin low. Table 13. Software Control Register MSB DB23 R/W DB22 0 1 1 2 LSB DB21 DB20 Register address 0 0 DB19 to DB3 Reserved DB2 DB1 Software control register data Reset CLR 1 DB0 LDAC 2 The CLR function has no effect when the LDAC pin is low. The LDAC function has no effect when the CLR pin is low. Table 14.
PAGE 23
Data Sheet AD5790 AD5790 FEATURES POWER-ON TO 0 V Unity-Gain Configuration The AD5790 contains a power-on reset circuit that, as well as resetting all registers to their default values, controls the output voltage during power-up. Upon power-on, the DAC is placed in tristate (its reference inputs are disconnected), and its output is clamped to AGND through a ~6 kΩ resistor. The DAC remains in this state until programmed otherwise via the control register.
PAGE 24
AD5790 Data Sheet Gain of Two Configuration (×2 Gain Mode) VREFP Rev. D | Page 24 of 28 A1 6.8kΩ 6.8kΩ R1 20-BIT DAC RFB RFB INV 10pF VOUT VOUT AD8675 ADA4898-1 ADA4004-1 AD5790 VREFN Figure 52. Output Amplifier in Gain of Two Configuration 10239-054 Figure 52 shows an output amplifier configured for a gain of two. The gain is set by the internal matched 6.
PAGE 25
Data Sheet AD5790 APPLICATIONS INFORMATION TYPICAL OPERATING CIRCUIT 10239-055 Figure 53. Typical Operating Circuit Rev.
PAGE 26
AD5790 Data Sheet Figure 53 shows a typical operating circuit for the AD5790 using an AD8675 as an output buffer. Because the output impedance of the AD5790 is 3.4 kΩ, an output buffer is required for driving low resistive, high capacitive loads. EVALUATION BOARD An evaluation board is available for the AD5790 to aid designers in evaluating the high performance of the part with minimum effort. The AD5790 evaluation kit includes a populated and tested AD5790 printed circuit board (PCB).
PAGE 27
Data Sheet AD5790 OUTLINE DIMENSIONS 2.75 2.65 2.50 4.00 BSC PIN 1 INDICATOR 20 PIN 1 INDICATOR 1 19 0.50 BSC 3.75 3.65 3.50 EXPOSED PAD 7 13 TOP VIEW 1.00 0.90 0.80 SEATING PLANE 0.30 0.25 0.20 0.50 0.40 0.30 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF 8 12 BOTTOM VIEW FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. 04-11-2012-B 5.00 BSC (Chamfer 0.225) 24 Figure 54.