Datasheet

ManualsBrandsANALOG DEVICES ManualsLinear ICsAD5932YRUZ

Programmable Frequency Scan

Waveform Generator

Data Sheet

AD5932

Rev. A

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FEATURES

Programmable frequency profile

No external components necessary

Output frequency up to 25 MHz

Burst-and-listen capability

Preprogrammable frequency profile minimizes number of

DSP/microcontroller writes

Sinusoidal/triangular/square wave outputs

Automatic or single pin control of frequency stepping

Power-down mode: 20 µA

Power supply: 2.3 V to 5.5 V

Automotive temperature range: −40°C to +125°C

16-lead, Pb-free TSSOP

APPLICATIONS

Frequency scanning/radar

Network/impedance measurements

Incremental frequency stimulus

Sensory applications

Proximity and motion

GENERAL DESCRIPTION

The AD5932

is a waveform generator offering a programmable

frequency scan. Utilizing embedded digital processing that

allows enhanced frequency control, the device generates

synthesized analog or digital frequency-stepped waveforms.

Because frequency profiles are preprogrammed, continuous

write cycles are eliminated, thereby freeing up valuable

DSP/microcontroller resources. Waveforms start from a known

phase and are incremented phase-continuously, which allows

phase shifts to be easily determined. Consuming only 6.7 mA,

the AD5932 provides a convenient low power solution to

waveform generation.

The AD5932 outputs each frequency in the range of interest for

a defined length of time and then steps to the next frequency in

the scan range. The length of time the device outputs a particular

frequency is preprogrammed, and the device increments the

frequency automatically; or, alternatively, the frequency is

incremented externally via the CTRL pin. At the end of the

range, the AD5932 continues to output the last frequency until

the device is reset. The AD5932 also offers a digital output via

the MSBOUT pin.

(continued on Page 3)

FUNCTIONAL BLOCK DIAGRAM

AD5932

DVDD CAP/2.5V DGND INTERRUPT ST

ANDBY AGND AVDD

VCC

2.5V

SYNC

MCLK

CTRL

FSYNC

SYNCOUT

MSBOUT

VOUT

COMP

SCLK SDATA

DATA AND CONTROL

FREQUENCY

CONTROLLER

INCREMENT

CONTROLLER

CONTROL

ON-BOARD

REFERENCE

FULL-SCALE

CONTROL

24-BIT

PIPELINED

DDS CORE

10-BIT

DAC

SERIAL INTERFACE

REGULATOR

DATA INCR

BUFFER

05416-001

Figure 1.

Protected by U.S. patent number 6747583.

Summary of content (28 pages)

PAGE 1
Programmable Frequency Scan Waveform Generator AD5932 Data Sheet FEATURES GENERAL DESCRIPTION Programmable frequency profile No external components necessary Output frequency up to 25 MHz Burst-and-listen capability Preprogrammable frequency profile minimizes number of DSP/microcontroller writes Sinusoidal/triangular/square wave outputs Automatic or single pin control of frequency stepping Power-down mode: 20 µA Power supply: 2.3 V to 5.
PAGE 2
AD5932 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Serial Interface ............................................................................ 15 Applications ....................................................................................... 1 Powering up the AD5932 .......................................................... 15 General Description ...........................................................
PAGE 3
Data Sheet AD5932 GENERAL DESCRIPTION (continued from Page 1) To program the AD5932, the user enters the start frequency, the increment step size, the number of increments to be made, and the time interval that the part outputs each frequency. The frequency scan profile is initiated, started, and executed by toggling the CTRL pin. Note that the AVDD and DVDD are independent of each other and can be operated from different voltages.
PAGE 4
AD5932 Data Sheet SPECIFICATIONS AVDD = DVDD = 2.3 V to 5.5 V; AGND = DGND = 0 V; TA = TMIN to TMAX, unless otherwise noted. Table 1.
PAGE 5
Data Sheet AD5932 Parameter Low Power Sleep Mode 1 2 Y Grade 1 Typ Min Max Unit 20 85 µA 140 240 µA Test Conditions/Comments Device is reset before putting into standby All outputs powered down, MCLK = 0 V, serial interface active All outputs powered down, MCLK active, serial interface active Operating temperature range is as follows: Y version: −40°C to +125°C; typical specifications are at +25°C. Guaranteed by design, not production tested.
PAGE 6
AD5932 Data Sheet TIMING SPECIFICATIONS All input signals are specified with tR = tF = 5 ns (10% to 90% of VDD) and are timed from a voltage level of (VIL + VIH)/2 (see Figure 3 to Figure 6). DVDD = 2.3 V to 5.5 V; AGND = DGND = 0 V; all specifications TMIN to TMAX, unless otherwise noted. Table 2.
PAGE 7
Data Sheet AD5932 t12 MCLK CTRL 05416-005 t11 VOUT t13 Figure 5. CTRL Timing CTRL t13 VOUT t14 SYNCOUT (End of Scan) t15 Figure 6. SYNCOUT Timing Rev.
PAGE 8
AD5932 Data Sheet ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 3. Parameter AVDD to AGND DVDD to DGND AGND to DGND CAP/2.5 V to DGND Digital I/O Voltage to DGND Analog I/O Voltage to AGND Operating Temperature Range Automotive (Y Version) Storage Temperature Range Maximum Junction Temperature TSSOP (4-Layer Board) θJA Thermal Impedance θJC Thermal Impedance Reflow Soldering (Pb-Free) Peak Temperature Time at Peak Temperature Rating −0.3 V to +6.0 V −0.3 V to +6.0 V −0.3 V to +0.
PAGE 9
Data Sheet AD5932 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS COMP 1 16 VOUT AVDD 2 15 AGND DVDD 3 14 STANDBY CAP/2.5V 4 DGND 5 13 FSYNC 12 SCLK SDATA MCLK 6 11 SYNCOUT 7 10 MSBOUT 8 9 CTRL INTERRUPT 05416-007 AD5932 TOP VIEW (Not to Scale) Figure 7. Pin Configuration Table 4. Pin Function Descriptions Pin No. 1 2 Mnemonic COMP AVDD 3 DVDD 4 CAP/2.
PAGE 10
AD5932 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS 9 –40 TA = 25°C AVDD = 5V MSBOUT, SYNCOUT ENABLED 8 –50 DVDD = 5V 7 SFDR (dBc) DVDD = 3V 4 –60 FOUT = MCLK/50 –65 –70 DVDD = 5V, FOUT = MCLK/7 3 –75 2 FOUT = MCLK/3 0 5 10 15 20 25 30 35 40 45 05416-008 DVDD = 3V, FOUT = MCLK/7 1 05416-011 –80 –85 –90 50 0 5 10 MCLK FREQUENCY (MHz) 20 25 30 35 40 45 50 MCLK FREQUENCY (MHz) Figure 8. Current Consumption (IDD) vs. MCLK Frequency Figure 11. Wide-Band SFDR vs.
PAGE 11
Data Sheet AD5932 70 90 TA = 25°C AVDD = DVDD = 5V fOUT = FMCLK/4096 65 80 NUMBER OF DEVICES 70 SNR (dB) 60 55 50 60 50 40 30 20 0 10M 20M 30M 40M 05416-017 10 0 50M MCLK FREQUENCY (MHz) 565 566 567 568 569 570 571 572 573 574 575 576 577 578 579 580 581 582 583 584 585 586 587 588 589 590 591 592 593 594 595 596 597 40 05416-014 45 V p-p (mV) Figure 14. SNR vs. MCLK Frequency Figure 17. Histogram of VOUT Peak-to-Peak 80 1.
PAGE 12
Data Sheet 0 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 –140 –150 –160 –170 100 –10 –20 –30 (dB) –40 –50 –60 –70 1k 10k 05416-023 –80 05416-020 PHASE NOISE AD5932 –90 –100 100k 0 5M RWB 1K FREQUENCY (Hz) VWB 300 ST 50 SEC FREQUENCY (Hz) Figure 23. fMCLK = 10 MHz, fOUT = 3.33 MHz = fMCLK/3, Frequency Word = 555555 Figure 20.
PAGE 13
AD5932 0 –10 –10 –20 –20 –30 –30 –40 –40 –50 –50 –60 –60 –70 –70 –80 –80 –90 –100 0 –90 –100 25M RWB 1K VWB 300 05416-028 (dB) 0 05416-026 (dB) Data Sheet 0 RWB 1K ST 200 SEC FREQUENCY (Hz) 25M VWB 300 ST 200 SEC FREQUENCY (Hz) Figure 26. fMCLK = 50 MHz, fOUT = 1.2 MHz, Frequency Word = 0624DD Figure 28. fMCLK = 50 MHz, fOUT = 7.
PAGE 14
AD5932 Data Sheet TERMINOLOGY Total Harmonic Distortion (THD) Total harmonic distortion is the ratio of the rms sum of harmonics to the rms value of the fundamental. For the AD5932, THD is defined as: Integral Nonlinearity (INL) Integral nonlinearity is the maximum deviation of any code from a straight line passing through the endpoints of the transfer function. The endpoints of the transfer function are zero scale and full scale. The error is expressed in LSBs.
PAGE 15
Data Sheet AD5932 THEORY OF OPERATION The AD5932 is a general-purpose, synthesized waveform generator capable of providing digitally programmable waveform sequences in both the frequency and time domain. The device contains embedded digital processing to provide a scan of a user-programmable frequency profile allowing enhanced frequency control. Because the device is preprogrammable, it eliminates continuous write cycles from a DSP/microcontroller in generating a particular waveform.
PAGE 16
AD5932 Data Sheet Table 5. Register Addresses PROGRAMMING THE AD5932 The AD5932 is designed to provide automatic frequency scans when the CTRL pin is triggered. The scan is controlled by a set of registers, the addresses of which are given in Table 5. The function of each register is described in more detail in the Setting Up the Frequency Scan section. The Control Register The AD5932 contains a 12-bit control register that sets up the operating modes, as shown in the following bit map.
PAGE 17
Data Sheet AD5932 SETTING UP THE FREQUENCY SCAN Number of Increments (NINCR) As stated in the Frequency Profile section, the AD5932 requires certain registers to be programmed to enable a frequency scan. The Setting Up the Frequency Scan section discusses these registers in more detail. An end frequency is not required on the AD5932.
PAGE 18
AD5932 Data Sheet Therefore, in this example, a time interval of 20 ns × 2047 = 40 µs is the maximum, with the minimum being 40 ns. For some applications, this maximum time of 40 µs may be insufficient. Therefore, to allow for sweeps that need a longer increment interval, time-base multipliers are provided. D12 and D11 are dedicated to the time-base multipliers, as shown in the bit map above. A more detailed table of the multiplier options is given in Table 9. Table 9.
PAGE 19
Data Sheet AD5932 The AD5932 offers a variety of outputs from the chip. The analog outputs are available from the VOUT pin and include a sine wave and a triangle output. The digital outputs are available from the MSBOUT pin and the SYNCOUT pin. Analog Outputs Sinusoidal Output The SIN ROM is used to convert the phase information from the frequency register into amplitude information, resulting in a sinusoidal signal at the output.
PAGE 20
AD5932 Data Sheet APPLICATIONS GROUNDING AND LAYOUT Interfacing to Microprocessors The printed circuit board that houses the AD5932 should be designed so that the analog and digital sections are separated and confined to certain areas of the board. This facilitates the use of ground planes that can be easily separated. A minimum etch technique is generally best for ground planes because it gives the best shielding. Digital and analog ground planes should be joined in only one place.
PAGE 21
Data Sheet AD5932 AD5932 TO 68HC11/68L11 INTERFACE Figure 35 shows the serial interface between the AD5932 and the 68HC11/68L11 microcontroller. The microcontroller is configured as the master by setting Bit MSTR in the SPCR to 1, which provides a serial clock on SCK while the MOSI output drives the serial data line, SDATA. Because the microcontroller does not have a dedicated frame sync pin, the FSYNC signal is derived from a port line (PC7).
PAGE 22
AD5932 Data Sheet EVALUATION BOARD The AD5932 evaluation board allows designers to evaluate the high performance AD5932 DDS modulator with minimum effort. The evaluation board interfaces to the USB port of a PC. It is possible to power the entire board from the USB port. All that is needed to complete the evaluation of the chip is either a spectrum analyzer or a scope. The DDS evaluation kit includes a populated and tested AD5932 printed circuit board.
PAGE 23
Data Sheet AD5932 05416-038 SCHEMATICS Figure 38. Page 1 of EVAL-AD5932EB Schematic Rev.
PAGE 24
Data Sheet 05416-039 AD5932 Figure 39. Page 2 of EVAL-AD5932EB Schematic Rev.
PAGE 25
Data Sheet AD5932 OUTLINE DIMENSIONS 5.10 5.00 4.90 16 9 4.50 4.40 4.30 6.40 BSC 1 8 PIN 1 1.20 MAX 0.15 0.05 0.20 0.09 0.30 0.19 0.65 BSC COPLANARITY 0.10 SEATING PLANE 8° 0° 0.75 0.60 0.45 COMPLIANT TO JEDEC STANDARDS MO-153-AB Figure 40.
PAGE 26
AD5932 Data Sheet NOTES Rev.
PAGE 27
Data Sheet AD5932 NOTES Rev.