Datasheet

AD71056
Rev. A | Page 13 of 20
POWER SUPPLY MONITOR
The AD71056 contains an on-chip power supply monitor. The
power supply (V
DD
) is continuously monitored by the AD71056.
If the supply is less than 4 V, the AD71056 becomes inactive.
This is useful to ensure proper device operation at power-up
and power-down. The power supply monitor has built-in
hysteresis and filtering that provide a high degree of immunity
to false triggering from noisy supplies.
In
Figure 21, the trigger level is nominally set at 4 V. The
tolerance on this trigger level is within ±5%. The power supply
and decoupling for the part should be such that the ripple at
V
DD
does not exceed 5 V ± 5% as specified for normal
operation.
V
DD
5V
4V
0V
TIME
INACTIVE ACTIVE INACTIVE
INTERNAL
A
CTIVATION
05636-021
Figure 21. On-Chip Power Supply Monitor
HPF and Offset Effects
Figure 22 illustrates the effect of offsets on the real power
calculation. As can be seen, offsets on Channel V1 and
Channel V2 contribute a dc component after multiplication.
Because this dc component is extracted by the LPF and used to
generate the real power information, the offsets contribute a
constant error to the real power calculation. This problem is
easily avoided by the built-in HPF in Channel V1. By removing
the offsets from at least one channel, no error component can
be generated at dc by the multiplication. Error terms at the line
frequency (ω) are removed by the LPF and the digital-to-
frequency conversion (see the
Digital-to-Frequency Conversion
section).
DC COMPONENT (INCLUDING ERROR TERM)
IS EXTRACTED BY THE LPF FOR REAL
POWER CALCULATION
I
OS
× V
V
OS
× I
V
OS
× I
OS
V× I
2
0
FREQUENCY (RAD/s)
05636-022
Figure 22. Effect of Channel Offset on the Real Power Calculation
Equation 6 shows how the power calculation is affected by the
dc offsets in the current and voltage channels.
(
)
{
}
(
)
{
}
OSOS
ItIVtV +ω
×
+
ω
coscos (6)
() ()
tVItIVIV
IV
OSOSOSOS
ω×+ω×+×+
×
= coscos
2
()
t
IV
ω×
×
+ 2cos
2
The HPF in Channel V1 has an associated phase response that
is compensated for on chip.
Figure 23 and Figure 24 show the
phase error between channels with the compensation network
activated. The AD71056 is phase compensated up to 1 kHz as
shown. This ensures correct active harmonic power calculation
even at low power factors.
FREQUENCY (Hz)
0.30
PHASE (Degrees)
0.25
0.20
0.15
0.10
0.05
0
–0.05
–0.10
0 100 200 300 400 500 600 700 800 900 1000
05636-023
Figure 23. Phase Error Between Channels (0 Hz to 1 kHz)
FREQUENCY (Hz)
0.30
PHASE (Degrees)
0.25
0.20
0.15
0.10
0.05
0
–0.05
–0.10
40 45 50 55 60 65 70
05636-024
Figure 24. Phase Error Between Channels (40 Hz to 70 Hz)