Datasheet

Data Sheet AD7176-2
Rev. A | Page 9 of 68
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Figure 4. Pin Configuration
Table 5. Pin Function Descriptions
Pin No. Mnemonic Description
1 AIN4 Analog Input 4. Selectable through crosspoint multiplexer.
2
REF−
Reference Input Negative Terminal. REF− can span from AVSS to AVDD1 − 1 V.
3 REF+ Reference Input Positive Terminal. An external reference can be applied between REF+ and REF−. REF+ can
span from AVDD1
to AVSS + 1 V. The part functions with a reference from 1 V to AVDD1.
4 REFOUT Buffered Output of Internal Reference. The output is 2.5 V with respect to AVSS.
5 REGCAPA Analog LDO Regulator Output. Decouple this pin to AVSS using a 1 µF capacitor.
6 AVSS Negative Analog Supply. This supply ranges from 0 V to −2.75 V and is nominally set to 0 V.
7 AVDD1 Analog Supply Voltage 1. This voltage is 5 V ± 10% with respect to AVSS.
8 AVDD2 Analog Supply Voltage 2. This voltage ranges from 2 V to AVDD1 with respect to AVSS.
9 XTAL1 Input 1 for Crystal.
10 CLKIO/XTAL2 Clock Input or Output (Based on the CLOCKSEL Bits in the ADCMODE Register)/Input 2 for Crystal. There
are four options available:
Internal oscillator—no output.
Internal oscillator—output to CLKIO/XTAL2. Operates at IOVDD logic level.
External clock—input to CLKIO/XTAL2. Input should be at IOVDD logic level.
External crystal—connected between XTAL1 and CLKIO/XTAL2.
11 DOUT/
RDY
Serial Data Output/Data Ready Output. DOUT/
RDY
serves a dual purpose. It functions as a serial data
output pin to access the output shift register of the ADC. The output shift register can contain data from
any of the on-chip data or control registers. The data-word/control word information is placed on the
DOUT/
RDY
pin on the SCLK falling edge and is valid on the SCLK rising edge. When
CS
is high, the
DOUT/
RDY
output is tristated. When
CS
is low, DOUT/
RDY
operates as a data ready pin, going low to
indicate the completion of a conversion. If the data is not read after the conversion, the pin goes high
before the next update occurs. The DOUT/
RDY
falling edge can be used as an interrupt to a processor,
indicating that valid data is available.
12 DIN Serial Data Input to the Input Shift Register on the ADC. Data in this shift register is transferred to the
control registers in the ADC, with the register address (RA) bits of the communications register identifying
the appropriate register. Data is clocked in on the rising edge of SCLK.
13 SCLK Serial Clock Input. This serial clock input is for data transfers to and from the ADC. The SCLK has a Schmitt-
triggered input, making the interface suitable for opto-isolated applications.
14
CS
Chip Select Input. This is an active low logic input used to select the ADC.
CS
can be used to select the ADC
in systems with more than one device on the serial bus.
CS
can be hardwired low, allowing the ADC to
operate in 3-wire mode with SCLK, DIN, and DOUT used to interface with the device. When
CS
is high, the
DOUT/
RDY
output is tristated.
1
2
3
4
5
6
7
8
9
10
12
11
REF–
REF+
REFOUT
AVDD1
AVSS
REGCAPA
AIN4
AVDD2
XTAL1
DIN
DOUT/RDY
CLKIO/XTAL2
20
21
22
23
24
19
18
17
16
15
14
13
AIN2
AIN1
AIN0
REGCAPD
GPIO0
GPIO1
DGND
IOVDD
SCLK
CS
SYNC/ERROR
AIN3
AD7176-2
TOP VIEW
(Not to Scale)
11037-004