Datasheet

AD7176-2 Data Sheet
Rev. A | Page 10 of 68
Pin No. Mnemonic Description
15
SYNC
/
ERROR
Can be switched between a logic input and a logic output in the GPIOCON register. When synchronization
input is enabled, this pin allows for synchronization of the digital filters and analog modulators when
using multiple AD7176-2
devices. When synchronization input is disabled, this pin can be used in one of
three modes:
Active low error input mode: this mode sets the ADC_ERROR bit in the STATUS register.
Active low, open-drain error output mode: the STATUS register error bits are mapped to the
ERROR
pin.
The
ERROR
pins of multiple devices can be wired together to a common pull-up resistor so that an error
on any device can be observed.
General-purpose output mode: the status of the pin is controlled by the ERR_DAT bit in the GPIOCON register.
The pin is referenced between IOVDD and DGND, as opposed to the AVDD1 and AVSS levels used by the
GPIO pins. The pin has an active pull-up in this case.
16 IOVDD Digital I/O Supply Voltage. IOVDD voltage ranges from 2 V to 5 V. IOVDD is independent of AVDD2. For
example, IOVDD can be operated at 3 V when AVDD2 equals 5 V, or vice versa. If AVSS is set to −2.5 V, the
voltage on IOVDD must not exceed 3.6 V.
17 DGND Digital Ground.
18 REGCAPD Digital LDO Regulator Output. This pin is for decoupling purposes only. Decouple this pin to DGND using a
1 µF capacitor.
19 GPIO0 General-Purpose Input/Output. The pin is referenced between AVDD1 and AVSS levels.
20 GPIO1 General-Purpose Input/Output. The pin is referenced between AVDD1 and AVSS levels.
21 AIN0 Analog Input 0. Selectable through the crosspoint multiplexer.
22 AIN1 Analog Input 1. Selectable through the crosspoint multiplexer.
23
AIN2
Analog Input 2. Selectable through the crosspoint multiplexer.
24 AIN3 Analog Input 3. Selectable through the crosspoint multiplexer.