Datasheet

AD7176-2 Data Sheet
Rev. A | Page 4 of 68
SPECIFICATIONS
AVDD1 = 4.5 V to 5.5 V, AVDD2 = 2 V to 5.5 V, IOVDD = 2 V to 5.5 V, AVSS = DGND = 0 V, REF+ = 2.5 V, REF− = AVSS,
internal master clock = 16 MHz, T
A
= T
MIN
to T
MAX
, unless otherwise noted.
Table 1.
Parameter Test Conditions/Comments Min Typ Max Unit
ADC SPEED AND PERFORMANCE
Output Data Rate (ODR) 5 250,000 SPS
No Missing Codes
1
24 Bits
Resolution See Table 6
Noise See Table 6
Noise Free Resolution 250 kSPS, REF+ = 5 V 17 Bits
2.5 kSPS, REF+ = 5 V 20 Bits
5 SPS, REF+ = 5 V 22 Bits
ACCURACY
Integral Nonlinearity (INL) 2.5 V reference ±2.5 ±7 ppm of FSR
5 V reference ±7 ppm of FSR
Offset Error
2
±40 µV
Offset Drift ±110 nV/°C
Offset Drift vs. Time
3
±450 nV/500 hours
Gain Error
2
25°C ±10 ±50 ppm/FSR
Gain Drift vs. Temperature
1
±0.5 ±1 ppm/FSR/°C
Gain Drift vs. Time
3
±3
ppm/FSR/
500 hours
REJECTION
Power Supply Rejection AVDD1, AVDD2 V
IN
= 1 V 90 dB
Common-Mode Rejection
At DC V
IN
= 0.1 V 95 dB
At 50 Hz and 60 Hz
1
20 SPS ODR (post filter)
(50 Hz ± 1 Hz and 60 Hz ± 1 Hz)
130 dB
Normal Mode Rejection
1
50 Hz ± 1 Hz and 60 Hz ± 1 Hz
Internal clock, 20 SPS ODR (post filter) 71 90 dB
External clock, 20 SPS ODR (post filter) 85 90 dB
ANALOG INPUTS
Differential Input Voltage Range ±V
REF
V
Absolute AIN Voltage Limits
1
AVSS − 0.050 AVDD1 + 0.05 V
Analog Input Current
Input Current ±48 µA/V
Input Current Drift External clock ±0.75 nA/V/°C
Internal clock (±2.5 % clock) ±4 nA/V/°C
Crosstalk 1 kHz input −120 dB
INTERNAL REFERENCE
100 nF external capacitor on
REFOUT to AVSS
Output Voltage REFOUT with respect to AVSS 2.5 V
Initial Accuracy
1
T
A
= 25°C − 0.16% + 0.16% V
Temperature Coefficient
0°C to +105°C ±2 ±5 ppm/°C
−40°C to +105°C ±3 ±10 ppm/°C
Reference Load Current, ILOAD I
L
−10 +10 mA
Power Supply Rejection (Line
Regulation)
AVDD1 and AVDD2
93 dB
Load Regulation V
OUT
/I
L
32 ppm/mA
Voltage Noise e
N
, 0.1 Hz to 10 Hz 4.5 µV rms
Voltage Noise Density e
N
, 1 kHz 215 nV/√Hz