4.8 kHz, Ultralow Noise, 24-Bit Sigma-Delta ADC with PGA and AC Excitation AD7195 FEATURES Chromatography PLC/DCS analog input modules Data acquisition Medical and scientific instrumentation AC or DC sensor excitation RMS noise: 8.5 nV at 4.7 Hz (gain = 128) 16 noise-free bits at 2.4 kHz (gain = 128) Up to 22.
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AD7195 TABLE OF CONTENTS Features .............................................................................................. 1 Overview ..................................................................................... 25 Interface ............................................................................................. 1 Analog Input Channel ............................................................... 26 Applications ........................................................................
AD7195 SPECIFICATIONS AVDD = 4.75 V to 5.25 V, DVDD = 2.7 V to 5.25 V, AGND = DGND = 0 V; REFIN(+) = AVDD, REFIN(−) = AGND, MCLK = 4.92 MHz, TA = TMIN to TMAX, unless otherwise noted. Table 1. Parameter ADC Output Data Rate No Missing Codes 2 Min Typ 4.7 1.17 1.56 24 24 Resolution RMS Noise and Output Data Rates Integral Nonlinearity Gain = 12 Gain > 1 Offset Error 4 , 5 ±1 ±5 ±75/gain ±0.5 ±100/gain Offset Error Drift vs. Temperature Offset Error Drift vs. Time ±5 ±5 25 Gain Error4 ±0.
AD7195 Parameter External Clock @ 50 Hz, 60 Hz @ 50 Hz @ 60 Hz ANALOG INPUTS Differential Input Voltage Ranges Min Typ 100 67 95 95 ±VREF/gain −(AVDD − 1.
AD7195 Parameter LOGIC INPUTS Input High Voltage, VINH2 Input Low Voltage, VINL2 Hysteresis2 Input Currents LOGIC OUTPUT (DOUT/RDY) Output High Voltage, VOH2 Output Low Voltage, VOL2 Output High Voltage, VOH2 Output Low Voltage, VOL2 Floating-State Leakage Current Floating-State Output Capacitance Data Output Coding SYSTEM CALIBRATION2 Full-Scale Calibration Limit Zero-Scale Calibration Limit Input Span POWER REQUIREMENTS 7 Power Supply Voltage AVDD − AGND DVDD − DGND Power Supply Currents AIDD Current DID
AD7195 TIMING CHARACTERISTICS AVDD = 4.75 V to 5.25 V, DVDD = 2.7 V to 5.25 V, AGND = DGND = 0 V, Input Logic 0 = 0 V, Input Logic 1 = DVDD, unless otherwise noted. Table 2.
AD7195 Circuit and Timing Diagram ISINK (1.6mA WITH DVDD = 5V, 100µA WITH DVDD = 3V) TO OUTPUT PIN 1.6V ISOURCE (200µA WITH DVDD = 5V, 100µA WITH DVDD = 3V) 08771-002 50pF Figure 2. Load Circuit for Timing Characterization CS (I) t6 t1 t5 MSB DOUT/RDY (O) LSB t7 t2 t3 08771-003 SCLK (I) t4 I = INPUT, O = OUTPUT Figure 3. Read Cycle Timing Diagram CS (I) t11 t8 SCLK (I) t9 t10 MSB LSB I = INPUT, O = OUTPUT Figure 4. Write Cycle Timing Diagram Rev.
AD7195 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. THERMAL RESISTANCE Table 3. θJA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages.
AD7195 32 31 30 29 28 27 26 25 CS SCLK MCLK2 MCLK1 DIN DOUT/RDY NC SYNC PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 2 3 4 5 6 7 8 AD7195 TOP VIEW (Not to Scale) 24 23 22 21 20 19 18 17 DVDD AVDD DGND AGND BPDSW NC REFIN(–) REFIN(+) NOTES 1. NC = NO CONNECT. 2. CONNECT EXPOSED PAD TO AGND. 08771-005 AIN1 AIN2 NC NC NC NC AIN3 AIN4 9 10 11 12 13 14 15 16 ACX2 ACX2 ACX1 ACX1 AVDD AGND NC AINCOM Figure 5.Pin Configuration Table 5. Pin Function Descriptions Pin No.
AD7195 Pin No. 20 21 22 23 24 25 Mnemonic BPDSW AGND DGND AVDD DVDD SYNC 26 27 NC DOUT/RDY 28 DIN 29 MCLK1 30 MCLK2 31 SCLK 32 CS Description Bridge Power-Down Switch to AGND. Analog Ground Reference Point. Digital Ground Reference Point. Analog Supply Voltage, 4.75 V to 5.25 V. AVDD is independent of DVDD. Digital Supply Voltage, 2.7 V to 5.25 V. DVDD is independent of AVDD.
AD7195 TYPICAL PERFORMANCE CHARACTERISTICS 8,388,760 30 8,388,758 25 8,388,756 FREQUENCY CODE 20 8,388,754 8,388,752 15 10 8,388,750 0 200 400 600 800 1000 SAMPLE 0 8,388,490 08771-006 8,388,746 8,388,576 8,388,662 8,388,748 CODE 8,388,834 8,388,920 08771-009 5 8,388,748 Figure 9. Noise Distribution Histogram (VREF = 5 V, Output Data Rate = 4800 Hz, Gain = 128, Chop Disabled, Sinc4 Filter) Figure 6. Noise (VREF = 5 V, Output Data Rate = 4.
AD7195 0 3.0 –0.1 2.0 OFFSET (µV) INL (ppm of FSR) –0.2 1.0 0 –0.3 –0.4 –1.0 –0.5 –2.0 –1.5 –1.0 –0.5 0 0.5 1.0 1.5 2.0 2.5 VIN (V) –0.7 –60 –40 –20 0 20 40 60 80 100 120 TEMERATURE (°C) Figure 12. INL (Gain = 1) 08771-015 –2.0 08771-012 –3.0 –2.5 –0.6 Figure 15. Offset Error (Gain = 128, Chop Disabled) 1.000008 6 1.000007 4 1.000005 GAIN INL (ppm of FSR) 1.000006 2 0 1.000004 1.000003 –2 1.000002 –4 0 0.005 0.010 0.015 0.020 VIN (V) 1.
AD7195 RMS NOISE AND RESOLUTION The tables in this section show the rms noise, peak-to-peak noise, effective resolution, and noise-free (peak-to-peak) resolution of the AD7195 for various output data rates and gain settings, with chop disabled and chop enabled for the sinc4 and sinc3 filters. The numbers given are for the bipolar input range with the external 5 V reference.
AD7195 SINC3 CHOP DISABLED Table 9. RMS Noise (nV) vs. Gain and Output Data Rate Filter Word (Decimal) 1023 640 480 96 80 32 16 5 2 1 Output Data Rate (Hz) 4.7 7.5 10 50 60 150 300 960 2400 4800 Settling Time (ms) 639.4 400 300 60 50 20 10 3.13 1.25 0.625 Gain of 1 290 470 610 1100 1200 1500 1950 4000 56,600 442,000 Gain of 8 125 135 145 160 170 230 308 590 7000 55,000 Gain of 16 53 56 58 86 95 130 175 330 3500 28,000 Gain of 32 24 29 32 50 55 80 110 200 1800 14,000 Gain of 64 10.
AD7195 SINC4 CHOP ENABLED Table 12. RMS Noise (nV) vs. Gain and Output Data Rate Filter Word (Decimal) 1023 640 480 96 80 32 16 5 2 1 Output Data Rate (Hz) 1.175 1.875 2.5 12.5 15 37.5 75 240 600 1200 Settling Time (ms) 1702 1067 800 160 133 53.3 26.7 8.33 3.33 1.67 Gain of 1 198 276 332 707 778 990 1344 2192 3606 9900 Gain of 8 85 92 99 127 141 156 191 325 523 1345 Gain of 16 41 45 46 61 62 85 106 184 297 680 Gain of 32 18 22 23 34 35 51 67 120 191 368 Gain of 64 7 8.
AD7195 SINC3 CHOP ENABLED Table 15. RMS Noise (nV) vs. Gain and Output Data Rate Filter Word (Decimal) 1023 640 480 96 80 32 16 5 2 1 Output Data Rate (Hz) 1.56 2.5 3.33 16.6 20 50 100 320 800 1600 Settling Time (ms) 1282 800 600 120 100 40 20 6.25 2.5 1.25 Gain of 1 205 332 431 778 849 1061 1379 2828 40,022 312,540 Gain of 8 88 95 103 113 120 163 218 417 4950 38,890 Gain of 16 37 40 41 61 67 92 124 233 2475 19,800 Gain of 32 17 21 23 35 39 57 78 141 1273 9900 Gain of 64 7.5 9 11.
AD7195 ON-CHIP REGISTERS The ADC is controlled and configured via a number of on-chip registers described on the following pages. In the following descriptions, the term set implies a Logic 1 state and cleared implies a Logic 0 state, unless otherwise noted. Table 18. Register Summary Register Communications Addr. 00 Dir.
AD7195 COMMUNICATIONS REGISTER (RS2, RS1, RS0 = 0, 0, 0) The communications register is an 8-bit write-only register. All communications to the part must start with a write operation to the communications register. The data written to the communications register determines whether the next operation is a read or a write operation and in which register this operation takes place.
AD7195 STATUS REGISTER (RS2, RS1, RS0 = 0, 0, 0; Power-On/Reset = 0x80) The status register is an 8-bit read-only register. To access the ADC status register, the user must write to the communications register, select the next operation to be a read, and load Bit RS2, Bit RS1, and Bit RS0 with 0. Table 21 outlines the bit designations for the status register. SR0 through SR7 indicate the bit locations, SR denoting that the bits are in the status register. SR7 denotes the first bit of the data stream.
AD7195 Table 22. Mode Register Bit Designations Bit Location MR23 to MR21 MR20 Bit Name MD2 to MD0 DAT_STA MR19, MR18 CLK1, CLK0 MR17, MR16 MR15 0 SINC3 MR14 MR13 0 ENPAR MR12 MR11 0 SINGLE MR10 REJ60 MR9 to MR0 FS9 to FS0 Description Mode select bits. These bits select the operating mode of the AD7195 (see Table 23). This bit enables the transmission of status register contents after each data register read.
AD7195 Table 23. Operating Modes MD2 0 MD1 0 MD0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 Mode Continuous conversion mode (default). In continuous conversion mode, the ADC continuously performs conversions and places the result in the data register. The DOUT/RDY pin and the RDY bit in the status register go low when a conversion is complete. The user can read these conversions by setting the CREAD bit in the communications register to 1, which enables continuous read.
AD7195 Table 24. Configuration Register Bit Designations Bit Location CON23 Bit Name CHOP CON22 ACX CON21 to CON16 CON15 to CON8 0 CH7 to CH0 CON7 BURN CON6 REFDET CON5 CON4 0 BUF CON3 U/B CON2 to CON0 G2 to G0 Description Chop enable bit. When the CHOP bit is cleared, chop is disabled. When the CHOP bit is set, chop is enabled. When chop is enabled, the offset and offset drift of the ADC are continuously removed. However, this increases the conversion time and settling time of the ADC.
AD7195 Table 25.
AD7195 FULL-SCALE REGISTER OFFSET REGISTER (RS2, RS1, RS0 = 1, 1, 1; Power-On/Reset = 0x5XXXX0) (RS2, RS1, RS0 = 1, 1, 0; Power-On/Reset = 0x800000) The offset register holds the offset calibration coefficient for the ADC. The power-on reset value of the offset register is 0x800000. The AD7195 has four offset registers; therefore, each channel has a dedicated offset register (see Table 25). Each of these registers is a 24-bit read/write register.
AD7195 ADC CIRCUIT INFORMATION AVDD AGND DVDD DGND REFIN(+) REFIN(–) REFERENCE DETECT AIN1 AIN2 AIN3 AIN4 AVDD MUX PGA AINCOM SERIAL INTERFACE AND CONTROL LOGIC Σ-Δ ADC DOUT/RDY DIN SCLK CS SYNC BPDSW AGND AC EXCITATION CLOCK AD7195 ACX1 ACX1 CLOCK CIRCUITRY ACX2 ACX2 MCLK1 MCLK2 08771-001 TEMP SENSOR Figure 18.
AD7195 The AD7195 has two differential/four pseudo differential analog input channels, which can be buffered or unbuffered. In buffered mode (the BUF bit in the configuration register is set to 1), the input channel feeds into a high impedance input stage of the buffer amplifier. Therefore, the input can tolerate significant source impedances and is tailored for direct connection to external resistive-type sensors such as strain gages or resistance temperature detectors (RTDs).
AD7195 registers is inhibited to avoid loading incorrect coefficients to these registers, and the ERR bit in the status register is set. If the user is concerned about verifying that a valid reference is in place every time a calibration is performed, the status of the ERR bit should be checked at the end of the calibration cycle. turned on, they flow in the external transducer circuit, and a measurement of the input voltage on the analog input channel can be taken.
AD7195 in ac excitation where resistor divider arrangements on the reference input add to the settling time associated with the switching. When the ACX bit in the configuration register is set to 0, the digital outputs ACX1 and ACX2 are high, while outputs ACX2 and ACX1 are low. Therefore, the bridge is dc excited with the T2 and T4 transistors turned on and the T1 and T3 transistors turned off.
AD7195 The serial interface can operate in 3-wire mode by tying CS low. In this case, the SCLK, DIN, and DOUT/RDY lines are used to communicate with the AD7195. The end of the conversion can be monitored using the RDY bit or pin. This scheme is suitable for interfacing to microcontrollers. If CS is required as a decoding signal, it can be generated from a port pin. For microcontroller interfaces, it is recommended that SCLK idle high between data transfers.
AD7195 Continuous Conversion Mode Continuous conversion is the default power-up mode. The AD7195 converts continuously, and the RDY bit in the status register goes low each time a conversion is complete. If CS is low, the DOUT/RDY line also goes low when a conversion is completed. To read a conversion, the user writes to the communications register, indicating that the next operation is a read of the data register. When the data-word has been read from the data register, DOUT/RDY goes high.
AD7195 Continuous Read conversion is complete, and the new conversion is placed in the output serial register. Rather than write to the communications register each time a conversion is complete to access the data, the AD7195 can be configured so that the conversions are placed on the DOUT/RDY line automatically.
AD7195 RESET The circuitry and serial interface of the AD7195 can be reset by writing consecutive 1s to the device; 40 consecutive 1s are required to perform the reset. This resets the logic, the digital filter, and the analog modulator, whereas all on-chip registers are reset to their default values. A reset is automatically performed on power-up. When a reset is initiated, the user must allow a period of 500 μs before accessing any of the on-chip registers.
AD7195 BRIDGE POWER-DOWN SWITCH In bridge applications, such as strain gauges and load cells, the bridge itself consumes the majority of the current in the system. For example, a 350 Ω load cell requires 15 mA of current when excited with a 5 V supply. To minimize the current consumption of the system, the bridge can be disconnected (when it is not being used) using the bridge power-down switch. Figure 50 shows how the bridge power-down switch is used.
AD7195 DIGITAL FILTER The AD7195 offers a lot of flexibility in the digital filter. The device has four filter options. The device can be operated with a sinc3 or sinc4 filter, chop can be enabled or disabled, and zero latency can be enabled. The option selected affects the output data rate, settling time, and 50 Hz/60 Hz rejection. The following sections describe each filter type, indicating the available output data rates for each filter option.
AD7195 When the analog input is constant or a channel change occurs, valid conversions are available at a constant output data rate. When conversions are being performed on a single channel and a step change occurs on the analog input, the ADC continues to output fully settled conversions if the step change is synchronized with the conversion process. If the step change is asynchronous, one conversion is output from the ADC, which is not completely settled (see Figure 27).
AD7195 The output data rate is 50 Hz when zero latency is disabled and 12.5 Hz when zero latency is enabled. Figure 31 shows the frequency response of the sinc4 filter. The filter provides 50 Hz ±1 Hz and 60 Hz ± 1 Hz rejection of 82 dB minimum, assuming a stable 4.92 MHz master clock. 0 f3dB = 0.272 × fADC Table 31 gives some examples of FS settings and the corresponding output data rates and settling times. Table 31.
AD7195 Sinc3 50 Hz/60 Hz Rejection The output data rate equals Figure 36 show the frequency response of the sinc3 filter when FS[9:0] is set to 96 and the master clock equals 4.92 MHz. The output data rate is equal to 50 Hz when zero latency is disabled and 16.7 Hz when zero latency is enabled. The sinc3 filter gives 50 Hz ± 1 Hz rejection of 95 dB minimum for a stable master clock. fADC = 1/tSETTLE = fCLK/(3 × 1024 × FS[9:0]) where: fADC is the output data rate. fCLK is the master clock (4.
AD7195 Simultaneous 50 Hz and 60 Hz rejection is obtained when FS[9:0] is set to 480 (master clock = 4.92 MHz), as shown in Figure 38. The output data rate is 10 Hz when zero latency is disabled and 3.3 Hz when zero latency is enabled. The sinc3 filter has rejection of 100 dB minimum at 50 Hz ± 1 Hz and 60 Hz ± 1 Hz. 0 –10 –20 FILTER GAIN (dB) –30 –40 CHOP ENABLED (SINC4 FILTER) With chop enabled, the ADC offset and offset drift are minimized. The analog input pins are continuously swapped.
AD7195 CH A CH A CH B CH B CH B CH B CH B 1/fADC Figure 41. Channel Change (Sinc4 Chop Enabled) –30 –40 –50 –60 –70 –80 –90 –100 When conversions are performed on a single channel and a step change occurs, the ADC does not detect the change in analog input; therefore, it continues to output conversions at the programmed output data rate. However, it is at least two conversions later before the output data accurately reflects the analog input.
AD7195 With chop enabled, the ADC offset and offset drift are minimized. The analog input pins are continuously swapped. With the analog input pins connected in one direction, the settling time of the sinc filter is allowed and a conversion is recorded. The analog input pins invert and another settled conversion is obtained. Subsequent conversions are averaged to minimize the offset.
AD7195 The 50 Hz/60 Hz rejection can be improved by setting the REJ60 bit in the mode register to 1. With FS[9:0] set to 96 and REJ60 set to 1, the filter response shown in Figure 49 is achieved. The output data rate is unchanged, but the 50 Hz/60 Hz ± 1 Hz rejection improves to 73 dB typically. 0 –10 –20 SUMMARY OF FILTER OPTIONS The AD7195 has several filter options.
AD7195 GROUNDING AND LAYOUT Because the analog inputs and reference inputs are differential, most of the voltages in the analog modulator are commonmode voltages. The high common-mode rejection of the part removes common-mode noise on these inputs. The analog and digital supplies to the AD7195 are independent and separately pinned out to minimize coupling between the analog and digital sections of the device.
AD7195 APPLICATIONS INFORMATION The AD7195 provides a low-cost, high resolution analog-todigital function. Because the analog-to-digital function is provided by a Σ-Δ architecture, the part is more immune to noisy environments, making it ideal for use in sensor measurement and industrial and process control applications. ACX2 and ACX2. In this phase, the excitation voltage to the bridge is reversed while the analog input signal and the reference voltage are also reversed.
AD7195 OUTLINE DIMENSIONS 0.30 0.25 0.18 32 25 0.50 BSC 0.80 0.75 0.70 0.50 0.40 0.30 8 16 9 BOTTOM VIEW 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF SEATING PLANE 3.65 3.50 SQ 3.45 EXPOSED PAD 17 TOP VIEW PIN 1 INDICATOR 1 24 0.25 MIN FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-220-WHHD. 112408-A PIN 1 INDICATOR 5.10 5.00 SQ 4.90 Figure 51.