Datasheet

AD7280A
Rev. 0 | Page 21 of 48
The 10 kΩ resistors in series with the inputs provide protection for
the analog inputs in the event of an overvoltage or undervoltage
on those inputs. The 100 nF capacitor across the differential inputs
acts as a low-pass filter in conjunction with the 10 kΩ resistor.
The cutoff frequency of the low-pass filter is 80 Hz. Using these
external components, the default acquisition time of 400 ns can
be used, which allows a combined acquisition and conversion
time of 1 µs.
CONVERTING CELL VOLTAGES AND AUXILIARY
ADC INPUTS IN A CHAIN OF AD7280As
The AD7280A provides a daisy-chain interface that allows up to
eight parts to be stacked without the need for individual isola-
tion. One feature of the daisy-chain interface is the ability to
initiate conversions on all parts in the daisy-chain stack with a
single convert start command. The convert start command is
transferred up the daisy chain, from the master device to each
AD7280A in turn. The delay time between each AD7280A is
t
DELAY
, as shown in Figure 34. The maximum delay between the
start of conversions on the master AD7280A and the last AD7280A
device in the chain can be determined by multiplying t
DELAY
by
the number of slave AD7280As in the daisy chain. The total
conversion time for all cell voltage and auxiliary ADC input
conversions can be calculated using the following equation:
Total Conversion Time = ((t
ACQ
+ t
CONV
) × (Number of
Conversions per Part)) − t
ACQ
+ ((N − 1) × t
DELAY
)
where:
t
ACQ
is the analog input acquisition time of the AD7280A (see
Table 9).
t
CONV
is the conversion time of the AD7280A, as specified in Tabl e 3.
Number of Conversions per Part is the number of inputs selected
for conversion (6, 9, or 12, as listed in Tabl e 8), multiplied by
the number of averages selected for each input (1, 2, 4, or 8).
N is the number of AD7280As in the daisy chain.
t
DELAY
is the delay time when transferring the convert start
command between adjacent AD7280A devices, as specified
in Tabl e 3.
The total conversion times calculated for three possible
configurations of the AD7280A are included in Table 10.
t
CONV
t
ACQ
+ t
CONV
VOLT 6 VOLT 5
TOTAL CONVERSION TIME =
((
t
ACQ
+ t
CONV
) × (#CONVERSIONS PER PART)) – t
ACQ
+ ((N – 1) × t
DELAY
)
VOLT 4 AUX6
t
DELAY
t
DELAY
t
DELAY
t
ACQ
+ t
CONV
t
DELAY
VOLT 12
VOLT 11 VOLT 10 AUX12
t
ACQ
+ t
CONV
VOLT 18
VOLT 17 VOLT 16 AUX18
INTERNAL AD
C
CONVERSIONS
PART 1
SERIAL READ
OPERATION
PART 2
SERIAL READ
OPERATION
PART 3
CNVST
09435-015
Figure 34. ADC Conversions and Readback on a Chain of Three AD7280As
Table 10. Calculated Conversion Times for Three Example AD7280A Configurations, T
A
= −40°C to +85°C
Bits
[D15:D14]
Bits
[D10:D9]
Bits
[D6:D5] Configuration
Conversion
Time per Part
Total Conversion Time
per 48 Channel Stack
00 00 00 12 channels; t
CONV
= 695 ns; t
ACQ
= 465 ns; average = 0 13.46 µs 15.2 µs
01 12 channels; t
CONV
= 695 ns; t
ACQ
= 1.01 µs; average = 0 19.45 µs 21.2 µs
10 12 channels; t
CONV
= 695 ns; t
ACQ
= 1.46 µs; average = 0 24.4 µs 26.15 µs
11 12 channels; t
CONV
= 695 ns; t
ACQ
= 1.89 µs; average = 0 29.13 µs 30.9 µs
10 00 00 6 channels; t
CONV
= 695 ns; t
ACQ
= 465 ns; average = 0 6.5 µs 8.23 µs
01 6 channels; t
CONV
= 695 ns; t
ACQ
= 1.01 µs; average = 0 9.22 µs 10.97 µs
10 6 channels; t
CONV
= 695 ns; t
ACQ
= 1.46 µs; average = 0 11.47 µs 13.22 µs
11 6 channels; t
CONV
= 695 ns; t
ACQ
= 1.89 µs; average = 0 13.62 µs 15.37 µs
00 11 00 12 channels; t
CONV
= 695 ns; t
ACQ
= 465 ns; average = 8 110.9 µs 112.65 µs
01 12 channels; t
CONV
= 695 ns; t
ACQ
= 1.01 µs; average = 8 162.67 µs 164.42 µs
10 12 channels; t
CONV
= 695 ns; t
ACQ
= 1.46 µs; average = 8 205.42 µs 207.17 µs
11 12 channels; t
CONV
= 695 ns; t
ACQ
= 1.89 µs; average = 8 246.27 µs 248.02 µs