Datasheet

AD7280A
Rev. 0 | Page 24 of 48
POWER-DOWN
The AD7280A provides two power-down options.
• Full power-down (hardware)
• Software power-down
Full Power-Down (Hardware)
The AD7280A can be placed into full power-down mode, which
requires only 5 µA maximum current, by taking the
PD
pin low.
The falling edge of the
PD
pin powers down all analog and
digital circuitry.
The AD7280A includes a digital delay filter on the
PD
pin,
which protects against a power-down being initiated by noise
or glitches on the hardware
PD
pin. A hardware power-down
is not initiated until the
PD
pin is held low for approximately
130 s. Similarly, the AD7280A is not taken out of power-down
mode until the
PD
pin is held high for approximately 130 s.
The digital delay filter does not apply on initial power-up. The
power-on request is accepted by the AD7280A approximately
5 s after the rising edge of
PD
.
When placing the AD7280A into full power-down mode, AV
CC
and DV
CC
must fall to 0 V and must not be held high by any
external means. AV
CC
and DV
CC
can be held high unintention-
ally if the auxiliary ADC inputs are greater than the forward
bias on the internal ESD protection diodes. For this reason, it
is recommended that the auxiliary ADC inputs return to 0 V
when the part is placed in full power-down mode.
In addition, all digital inputs on the AD7280A master device
must return to 0 V when the part is placed in full power-down
mode (see Figure 37). However, if an external V
DRIVE
supply is
used—that is, V
DRIVE
is not connected to V
REG
—then only the
CNVST
line must return low (see ). Figure 38
When the AD7280A is placed into full power-down mode, the
device must be left in full power-down for a minimum of 2 ms
when the V
REG
and V
REF
pins are decoupled with 1 F capacitors.
This ensures that the charge on the V
REG
and V
REF
decoupling
capacitors dissipates sufficiently to allow the internal power-on
reset circuit to activate when powering the AD7280A back up.
This time is measured from the falling edge of the
PD
pin.
shows a plot of the voltage on the V
REG
and V
REF
pins
as the AD7280A is powering down with 1 F decoupling
capacitors on the pins. shows a similar plot but with
10 F decoupling capacitors on the V
REG
and V
REF
pins.
Figure 18
Figure 20
V
SS
AD7280A
V
REG
0.1µF 10µF
1µF
0.1µF
0.1µF
V
DD
V
DD
DV
CC
AV
CC
1µF
0.1µF
V
REF
C
REF
ALERT
SDO
SCLK
SDI
V
DRIVE
MASTER
AUX6
AUX
TERM
AUX5
AUX4
AUX3
AUX2
AUX1
10kΩ
MUST GO TO 0V IN
HARDWARE POWER-DOWN
MUST GO TO 0V
IN HARDWARE
POWER-DOWN
CS
PD
CNVST
DSP/MICRO-
PROCESSOR
09435-023
Figure 37. V
DRIVE
Powered from V
REG
V
SS
AD7280A
V
REG
0.1µF 10µF
1µF
0.1µF
0.1µF
V
DD
V
DD
10µF0.1µF
DV
CC
AV
CC
1µF
0.1µF
V
REF
C
REF
ALERT
SDO
SCLK
SDI
V
DRIVE
MASTER
AUX6
AUX
TERM
AUX5
AUX4
AUX3
AUX2
AUX1
10kΩ
MUST GO TO 0V IN
HARDWARE POWER-DOWN
MUST GO TO 0V
IN HARDWARE
POWER-DOWN
CS
PD
CNVST
DSP/MICRO-
PROCESSOR
2.7V TO 5.5V SUPPLY
09435-024
Figure 38. V
DRIVE
Powered from DSP/Microprocessor