Datasheet

AD7280A
Rev. 0 | Page 25 of 48
Software Power-Down
The AD7280A can be placed into software power-down mode,
which requires 3.8 mA of current, by setting Bit D8 in the
control register through the serial interface. The
CNVST
pin
should be gated out before generating a software power-down
(see the
CNVST
Control Register section). When the AD7280A
is powered down through the serial interface, the regulator, the
reference, and the daisy-chain circuitry stay powered up, but the
remaining analog and digital circuitry is powered down. This is
necessary to ensure that the signal to power on the part, or the
chain of parts, is correctly received.
Power-Down Timer
The PD timer register allows the user to program a set time after
which the AD7280A is automatically powered down. This timer
functions as a time delay between the falling edge of the
PD
input (or the setting of Bit D8 in the control register) and the
AD7280A powering down. The PD timer can be set to a value
from 0 minutes to 36.9 minutes, with a resolution of 71.5 sec.
The user should first write to the PD timer register to define the
desired delay. Any subsequent falling edge on the
PD
input or
setting of Bit D8 in the control register starts the PD timer.
When the programmed time elapses, the AD7280A checks the
state of the
PD
pin. If the
PD
pin is low, the AD7280A powers
down. If the
PD
pin is high, the part does not power down and
continues to operate as normal. The default value of the PD
timer register on power-up is 0x00.
If the PD timer register is written to after the counter starts,
the counter is reset to 0. The count then restarts automatically,
without further input from the user, and counts to the new value
in the PD timer register. If the new time in the PD timer register
is 0, the part checks the state of the
PD
pin and powers down if
the
PD
pin is low. Note that when the PD timer is activated—for
example, by a falling edge on the
PD
pin—a subsequent rising
edge on the
PD
pin does not disable the active PD timer. It is
recommended that the
PD
pin be held low until an active PD
timer expires.
POWER-UP TIME
As described in the Power-Down section, a full power-down
of the AD7280A (active low on the
PD
input) powers down all
analog and digital circuitry. The recommended power-up time
from hardware power-down, when the internal reference is
decoupled with a 1 µF capacitor, is 5.5 ms. It is recommended
that no conversions be initiated until the 5.5 ms power-up time
elapses because such conversions can result in inaccurate data.
A software power-down powers down all analog and digital
circuitry on the AD7280A except for the regulator, the 1.2 V
band gap reference, and the daisy-chain circuitry. The recom-
mended power-up time from software power-down, when the
V
REF
pin is decoupled with a 1 µF capacitor, is 1 ms.
CELL BALANCING OUTPUTS
The AD7280A provides six cell balance outputs that can be used
to drive the gate of external transistors as part of a cell balancing
circuit. Each CBx output can be set to provide either a 0 V or 5 V
output with respect to the absolute amplitude of the negative
terminal of the battery cell that is being balanced. For example,
the CB6 output provides a 0 V or 5 V output with respect to the
voltage on the VIN5 analog input. The CBx outputs are set by
writing to the cell balance register. The default value of the cell
balance register on power-up is 0x00.
VIN6
CB6
VIN5
CB5
VIN4
CB4
VIN3
CB3
VIN2
CB2
VIN1
CB1
VIN0
AD7280A
10kΩ
10kΩ
10kΩ
10kΩ
10kΩ
10kΩ
09435-019
Figure 39. Cell Balancing Configuration
As noted in the Power-Down Timer section, a power-down timer
can be programmed on the AD7280A. This timer can be used
to allow cell balancing to occur for a set time before powering
down the AD7280A. The power-down timer is independent of
the cell balance timers. If no power-down timer is set—that is, if
the PD timer register is at its default value of 0x00—a falling edge
on the
PD
pin switches off the CBx outputs and powers down the
AD7280A. If a power-down timer is set, the CBx outputs are
powered down when the programmed power-down timer elapses
and the AD7280A is powered down.
In an application with two or more AD7280A devices in a daisy
chain, it is recommended that series resistors be placed between
the CBx outputs of the AD7280A and the gates of the external
cell balancing transistors. These resistors are recommended to
protect the AD7280A in the event that the external cell balancing
transistors are damaged during the initial connection of the
monitoring circuitry to the battery stack. Consideration should
also be given to the protection of these external transistors
during the initial connection of the monitoring circuitry to the
battery stack.