Datasheet

AD7280A
Rev. 0 | Page 44 of 48
EMC GUIDELINES
SCHEMATIC AND LAYOUT GUIDELINES
To optimize the performance of a chain of AD7280A devices
under noisy conditions—for example, when experiencing
electromagnetic interference—the following schematic and
layout guidelines should be observed (see Figure 29).
1.
All AD7280A devices in a daisy chain should be physically
located on a single printed circuit board (PCB). Daisy-
chain connections between PCBs are not recommended.
Individual PCBs can be used for separate daisy chains. In
this case, however, communication between PCBs is via a
communication protocol such as SPI or CAN.
2.
Individual 22 pF capacitors should be placed on each
daisy-chain connection. The capacitors should be
terminated to either the V
SS
pin of the upper device or the
V
DD
pin of the lower device, depending on the direction in
which data is flowing in the daisy chain. The
PD
,
CS
,
SCLK, SDI, and
CNVST
daisy-chain connections pass data
up the chain. The 22 pF capacitors on these pins should be
terminated to the V
SS
pin of the upper device in the chain.
The SDOlo and ALERTlo daisy-chain connections pass
data down the chain. The 22 pF capacitors on these pins
should be terminated to the V
DD
pin of the lower device in
the chain.
3.
A direct, low impedance trace should connect the V
DD
pin
of the lower device with the V
SS
pin of the upper device. The
AD7280A daisy-chain connections operate at the V
DD
/V
SS
voltage of the adjacent AD7280As. Ensuring a low imped-
ance path between the supplies optimizes the performance
of the daisy-chain communications.
4.
The application PCB should have a minimum of four
layers. The AD7280A daisy-chain connections should be
routed on an inner layer of the PCB.
5.
The AD7280A daisy-chain connections should be shielded
above and below by a V
SS
supply plane connected to the V
SS
pin of the upper device in the chain. The shield should extend
from the V
SS
and daisy-chain low pins of the upper device
(Pin 15, Pin 17, and Pin 21 to Pin 28) to cover the daisy-
chain high pins of the lower device (Pin 42 to Pin 48), as
well as a low impedance trace to the V
DD
pin. This shield
provides maximum protection to the daisy-chain connec-
tions when operating in a noisy environment.
6.
The AD7280A devices should be placed as close together
as possible on the PCB to minimize the length of the daisy-
chain connections.
7.
To minimize noise reaching the V
DD
/V
SS
pins of the
AD7280A, ferrite beads should be inserted into the V
DD
and V
SS
supply traces coming from the battery. These beads
can be inserted into the PCB traces between the battery cell
connection on the PCB and the individual supply pins.
Note that these ferrite beads can be replaced with a small value
of resistance. The maximum value of resistance that can be
used is 20 Ω. A resistor should not be included on the V
SS
line to the master chip. Instead, a direct connection should
be made from the battery cell connector to the V
SS
pin.
Analog Devices, Inc., also recommends the following:
• Inclusion of a 100 nF capacitor across the six individual cells
that are monitored by the AD7280A. This capacitor should
be placed physically close to the battery cell connector on
the PCB.
• Correct termination of all unused pins on the device. More
information about the correct termination of unused pins
can be found in the Pin Configuration and Function
Descriptions section.
OPERATION IN A NOISY ENVIRONMENT
When the AD7280A is operating in a noisy environment—for
example, when electromagnetic interference is experienced—
glitches can occur on the SPI or daisy-chain inputs and outputs.
To limit the effect that such glitches may have on the operation
of the AD7280A, each daisy-chain input is passed through a
filter before being applied internally within the device. The filter
on the
PD
pin is 130 µs wide (see the section for
more information). The filter on the remaining daisy-chain
inputs (
Power-Down
CS
, SCLK, SDI,
CNVST
, SDIhi, and ALERThi) is 150 ns
wide. Glitches wider than these values on any of the pins can
have an effect on the AD7280A, and care should be taken to
ensure correct operation.
Glitches that occur on the SCLK and
CS
pins can result in the
AD7280A losing synchronization with the DSP/microprocessor.
However, such a loss of synchronization affects only the 32-bit
word during which the glitch occurred. The AD7280A interface
is reset on the rising edge of
CS
to ensure that the part is resyn-
chronized, as described in the section. Serial Interface
Glitches that occur on the SDI or SDOhi pin can result in a
change of state of any of the bits in the 32-bit words that are
written to or read from the chain of AD7280As. In this event,
the 8-bit CRC received by the AD7280A or by the DSP/micro-
processor should not match the CRC that is calculated based
on the 32-bit word that was transmitted.
Glitches that occur on the ALERThi pin are observed on the
alert signal when output from the master device. Care should
be taken when designing the alert response software or hard-
ware to ensure that such glitches are treated appropriately in
the system.
Glitches that occur on the
CNVST
pin may be interpreted as a
conversion start request. If this occurs during a read operation,
it can result in incorrect data being read back from the AD7280A.