Datasheet

AD7280A
Rev. 0 | Page 45 of 48
If a second convert start signal is received by the AD7280A while
the conversion results are being read back, the data being read
back from the device, or chain of devices, can be corrupted. The
corruption of data occurs at the point in which the second con-
vert start signal is introduced. Any data read back prior to the
second convert start signal is correct, but data read back after
the second convert start signal may be corrupted.
Note that the corruption of data is not limited to the conversion
result. The device address, channel address, and CRC data can
also be corrupted. The
CNVST
control register should be used
to gate the convert start signal. This prevents any glitches that
occur on the
CNVST
pin from being applied directly to the
internal circuitry of the AD7280A.
SOFTWARE FLOWCHART
See Figure 41 for a software flowchart of a suggested sequence
of steps that should be considered when operating the
AD7280A in a noisy environment.
09435-028
HAS THE
REQUIRED NUMBER
OF CONVERSIONS BEEN
COMPLETED?
YES
NO
WAIT AT LEAST 5.5ms FOR ALL DEVICES
TO BE FULLY POWERED UP
POWER UP AD7280A
CHAIN OF DEVICES
INITIALIZE DEVICE IDs ON ALL
PARTS IN THE CHAIN
WRITE TO CONTROL REGISTER
TO RETURN DB1/DB2 TO
DEFAULT VALUES
PROGRAM CONFIGURATION
REGISTERS AS REQUIRED
INITIATE A
CONVERSION
WRITE TO CNVST CONTROL
REGISTER TO ALLOW A SINGLE
CNVST PULSE THROUGH
READ BACK THE CONVERSION RESULTS FROM ALL DEVICES IN
THE DAISY-CHAIN READBACK MODE
CHECK
INTEGRITY OF
CHAIN INITIALIZATION
BY READING BACK THE LOW
BYTE OF THE CONTROL
REGISTER FROM
ALL DEVICES
IS THE
CRC CORRECT
FOR ALL DATA FRAMES
READ BACK?
HAVE ANY
PARTS IN THE
CHAIN RETURNED A
RESULT OF ALL 0s FROM
THE CONTROL
REGISTER?
OK
NO
NOT
OK
YES
IGNORE RESPECTIVE
32-BIT FRAME
DATA VALIDATION
COMPLETE
NO
YES
POWER DOWN AD7280A
CHAIN OF DEVICES
PLACE CHAIN IN POWER-DOWN MODE AND
WAIT AT LEAST 2ms FOR CAPACITORS ON
V
REG
AND V
REF
TO DISSIPATE CHARGE
Figure 41. Suggested Software Flowchart When Operating in a Noisy Environment