Datasheet

Data Sheet AD7329
Rev. B | Page 19 of 40
D
D
V
DD
ADC
IN
–MUX
OUT
–
C2
R1
V
IN
–
V
SS
C1 C3 C4
05402-030
D
D
V
DD
ADC
IN
+MUX
OUT
+
C2
R1
V
IN
+
V
SS
C1 C3 C4
Figure 31. Equivalent Analog Input Circuit, Differential Mode
Care should be taken to ensure that the analog input does not
exceed the V
DD
and V
SS
supply rails by more than 300 mV.
Exceeding this value causes the diodes to become forward
biased and to start conducting into either the V
DD
supply rail or
the V
SS
supply rail. These diodes can conduct up to 10 mA
without causing irreversible damage to the part.
In Figure 30 and Figure 31, Capacitor C1 is typically 4 pF and
can primarily be attributed to pin capacitance. Resistor R1 is a
lumped component made up of the on resistance of the input
multiplexer and the track-and-hold switch. Capacitor C2 is the
sampling capacitor; its capacitance varies depending on the
analog input range selected (see the Specifications section).
TRACK-AND-HOLD SECTION
The track-and-hold on the analog input of the AD7329 allows
the ADC to accurately convert an input sine wave of full-scale
amplitude to 13-bit accuracy. The input bandwidth of the track-
and-hold is greater than the Nyquist rate of the ADC. The
AD7329 can handle frequencies up to 20 MHz.
The ADC
IN
pins connect directly to the input stage of the track-
and-hold circuit. This is a high impedance input. Connecting
the MUX
OUT
pins directly to the ADC
IN
pins connects the
multiplexer output to the track-and-hold circuit. The input
voltage range on the ADC
IN
pins is determined by the range
register bits for the input channel selected. The user must
ensure that the input voltage to the ADC
IN
pins is within the
selected voltage range.
The track-and-hold enters its tracking mode on the 14
th
SCLK
rising edge after the
CS
falling edge. The time required to
acquire an input signal depends on how quickly the sampling
capacitor is charged. With zero source impedance, 300 ns is
sufficient to acquire the signal to the 13-bit level.
The acquisition time required is calculated using the following
formula:
t
ACQ
= 10 × ((R
SOURCE
+ R)C)
where C is the sampling capacitance, and R is the resistance
seen by the track-and-hold amplifier looking at the input.
For the AD7329, the value of R includes the on resistance of the
input multiplexer and is typically 300 Ω. R
SOURCE
should include
any extra source impedance on the analog input.
The AD7329 enters track mode on the 14
th
SCLK rising edge.
When the AD7329 is run at a throughput rate of 1 MSPS with
a 20 MHz SCLK signal, the ADC has approximately 1.5 SCLK
periods plus t
8
and the quiet time, t
QUIET
, to acquire the analog
input signal. The ADC goes back into hold mode on the
CS
falling edge.
The current required to drive the ADC is extremely small when
using the external op amp between the MUX
OUT
and ADC
IN
pins. This is due to the high input impedance of the op amp
placed between the MUX
OUT
and ADC
IN
pins. This can be seen
in Figure 32, where the current required to drive the AD7329
input is <0.2 μA when AD8021 is placed between the MUX
OUT
and ADC
IN
pins.
0.20
0.14
0
1000
05402-056
THROUGHPUT RATE (kSPS)
INPUT CURRENT (µA)
0.19
0.18
0.17
0.16
0.15
100 200 300 400 500 600 700 800 900
V
DD
= 12V, V
SS
= –12V
V
CC
= V
DRIVE
= 5V
SINGLE-ENDED MODE
50kHz ON SELECTED CHANNEL
f
IN
= 50kHz
T
A
= 25°C
AD8021 BETWEEN MUX
OUT
AND ADC
IN
PINS
Figure 32. Input Current vs. Throughput Rate
with AD8021 Between MUX
OUT
and ADC
IN
35
0
0
1000
05402-057
THROUGHPUT RATE (kSPS)
INPUT CURRENT (µA)
100 200 300 400 500 600 700 800 900
V
DD
= 12V, V
SS
= –12V
V
CC
= V
DRIVE
= 5V
SINGLE-ENDED MODE
50kHz ON SELECTED CHANNEL
f
IN
= 50kHz
T
A
= 25°C
WIRE LINK BETWEEN MUX
OUT
AND ADC
IN
PINS
30
25
20
15
10
5
Figure 33. Input Current vs. Throughput Rate
with a Wire Link Between MUX
OUT
and ADC
IN