Datasheet

ManualsBrandsANALOG DEVICES ManualsLinear ICsLinear IC - Op-amp J-FET SOIC 16

REV. D

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AD745

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781/329-4700 www.analog.com

Fax: 781/326-8703 © Analog Devices, Inc., 2002

Ultralow Noise,

High Speed, BiFET Op Amp

CONNECTION DIAGRAM

FEATURES

ULTRALOW NOISE PERFORMANCE

2.9 nV/冑 Hz at 10 kHz

0.38 V p-p, 0.1 Hz to 10 Hz

6.9 fA/冑Hz Current Noise at 1 kHz

EXCELLENT AC PERFORMANCE

12.5 V/s Slew Rate

20 MHz Gain Bandwidth Product

THD = 0.0002% @ 1 kHz

Internally Compensated for Gains of +5 (or –4) or

Greater

EXCELLENT DC PERFORMANCE

0.5 mV Max Offset Voltage

250 pA Max Input Bias Current

2000 V/mV Min Open Loop Gain

Available in Tape and Reel in Accordance with

EIA-481A Standard

APPLICATIONS

Sonar

Photodiode and IR Detector Amplifiers

Accelerometers

Low Noise Preamplifiers

High Performance Audio

PRODUCT DESCRIPTION

The AD745 is an ultralow noise, high-speed, FET input opera-

tional amplifier. It offers both the ultralow voltage noise and

high speed generally associated with bipolar input op amps and

the very low input currents of FET input devices. Its 20 MHz

bandwidth and 12.5 V/µs slew rate makes the AD745 an ideal

SOURCE RESISTANCE – 

1000

100

INPUT NOISE VOLTAGE – nV/ Hz

100

1k 10k 100k 1M 10M

SOURCE

OP37 AND

RESISTOR

AD745 AND

RESISTOR

AD745 AND RESISTOR

OP37 AND RESISTOR

RESISTOR NOISE ONLY

Figure 1.

amplifier for high-speed applications demanding low noise and

high dc precision. Furthermore, the AD745 does not exhibit an

output phase reversal.

The AD745 also has excellent dc performance with 250 pA

maximum input bias current and 0.5 mV maximum offset voltage.

The internal compensation of the AD745 is optimized for higher

gains, providing a much higher bandwidth and a faster slew

rate. This makes the AD745 especially useful as a preamplifier

where low level signals require an amplifier that provides both

high amplification and wide bandwidth at these higher gains.

The AD745 is available in two performance grades. The AD745J

and AD745K are rated over the commercial temperature range

of 0°C to 70°C, and are available in the 16-lead SOIC package.

FREQUENCY – Hz

120

100

OPEN-LOOP GAIN – dB

100

–20

1k 10k 100k 1M 10M 100M

120

100

–20

PHASE MARGIN – Degrees

GAIN

PHASE

Figure 2.

16-Lead SOIC (R) Package

Summary of content (12 pages)

PAGE 1
a Ultralow Noise, High Speed, BiFET Op Amp AD745 FEATURES ULTRALOW NOISE PERFORMANCE 2.9 nV/冑Hz at 10 kHz 0.38 V p-p, 0.1 Hz to 10 Hz 6.9 fA/冑Hz Current Noise at 1 kHz CONNECTION DIAGRAM 16-Lead SOIC (R) Package EXCELLENT AC PERFORMANCE 12.5 V/ s Slew Rate 20 MHz Gain Bandwidth Product THD = 0.0002% @ 1 kHz Internally Compensated for Gains of +5 (or –4) or Greater EXCELLENT DC PERFORMANCE 0.
PAGE 2
AD745–SPECIFICATIONS AD745 ELECTRICAL CHARACTERISTICS Model Conditions INPUT OFFSET VOLTAGE 1 Initial Offset Initial Offset vs. Temp. vs. Supply (PSRR) vs. Supply (PSRR) INPUT BIAS CURRENT 3 Either Input Either Input @ TMAX Either Input Either Input, VS = ± 5 V INPUT OFFSET CURRENT Offset Current @ TMAX FREQUENCY RESPONSE Gain BW, Small Signal Full Power Response Slew Rate Settling Time to 0.01% Total Harmonic Distortion4 Min INPUT VOLTAGE NOISE AD745J Typ 0.
PAGE 3
AD745 ABSOLUTE MAXIMUM RATINGS 1 ESD SUSCEPTIBILITY Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 18 V Internal Power Dissipation2 SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 W Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± VS Output Short-Circuit Duration . . . . . . . . . . . . . . . . Indefinite Differential Input Voltage . . . . . . . . . . . . . . . . . .
PAGE 4
AD745 –Typical Performance Characteristics 20 35 20 15 +VIN 10 –VIN 5 0 15 POSITIVE SUPPLY 10 NEGATIVE SUPPLY 5 0 20 0 TPC 1. Input Voltage Swing vs. Supply Voltage INPUT BIAS CURRENT – Amps 12 9 6 3 0 5 10 15 SUPPLY VOLTAGE VOLTS 0 –9 –6 –3 0 3 6 9 COMMON-MODE VOLTAGE – V TPC 7. Input Bias Current vs. Common-Mode Voltage 12 15 10 5 100 1k LOAD RESISTANCE – 10k 10–6 200 100 10–7 10–8 10–9 10–10 10 1 CLOSED LOOP GAIN = –5 0.
PAGE 5
AD745 14 120 150 RL = 2k 100 SLEW RATE – V/ s 60 40 GAIN 20 OPEN-LOOP GAIN – dB OPEN-LOOP GAIN – dB PHASE 80 12 CLOSED-LOOP GAIN = 5 10 140 130 120 100 0 –20 100 1k 10k 100k 1M FREQUENCY – Hz 10M 8 –60 –40 –20 0 20 40 60 80 100 110 120 TEMPERATURE – C 100M TPC 10. Open-Loop Gain and Phase vs. Frequency TPC 11. Slew Rate vs. Temperature 0 10 15 5 SUPPLY VOLTAGE VOLTS 20 TPC 12. Open-Loop Gain vs.
PAGE 6
AD745 648 72 TOTAL UNITS = 760 540 54 486 48 42 36 30 24 432 378 324 270 216 18 162 12 108 6 54 0 –15 0 2.6 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 INPUT VOLTAGE NOISE @ 10kHz – nV Hz –5 0 5 10 –10 15 INPUT OFFSET VOLTAGE DRIFT – V/ C TPC 19. Distribution of Offset Voltage Drift. TA = 25°C to 125°C TOTAL UNITS = 4100 594 60 NUMBER OF UNITS NUMBER OF UNITS 66 TPC 20. Typical Input Noise Voltage Distribution @ 10 kHz TPC 21.
PAGE 7
AD745 OP AMP PERFORMANCE JFET VERSUS BIPOLAR The AD745 offers the low input voltage noise of an industry standard bipolar opamp without its inherent input current errors. This is demonstrated in Figure 3, which compares input voltage noise vs. input source resistance of the OP37 and the AD745 opamps. From this figure, it is clear that at high source impedance the low current noise of the AD745 also provides lower total noise.
PAGE 8
AD745 Figures 5 and 6 show two ways to buffer and amplify the output of a charge output transducer. Both require the use of an amplifier that has a very high input impedance, such as the AD745. Figure 5 shows a model of a charge amplifier circuit. Here, amplification depends on the principle of conservation of charge at the input of amplifier A1, which requires that the charge on capacitor CS be transferred to capacitor CF, thus yielding an output voltage of ∆Q/CF.
PAGE 9
AD745 HOW CHIP PACKAGE TYPE AND POWER DISSIPATION AFFECT INPUT BIAS CURRENT 300 TA = 25 C INPUT BIAS CURRENT – Amps As with all JFET input amplifiers, the input bias current of the AD745 is a direct function of device junction temperature, IB approximately doubling every 10°C. Figure 9 shows the relationship between bias current and junction temperature for the AD745. This graph shows that lowering the junction temperature will dramatically improve IB.
PAGE 10
AD745 TWO HIGH PERFORMANCE ACCELEROMETER AMPLIFIERS Two of the most popular charge-out transducers are hydrophones and accelerometers. Precision accelerometers are typically calibrated for a charge output (pC/g).* Figures 14 and 15 show two ways in which to configure the AD745 as a low noise charge amplifier for use with a wide variety of piezoelectric accelerometers.
PAGE 11
AD745 DESIGN CONSIDERATIONS FOR I-TO-V CONVERTERS 1 F + There are some simple rules of thumb when designing an I-V converter where there is significant source capacitance (as with a photodiode) and bandwidth needs to be optimized. Consider the circuit of Figure 18. The high frequency noise gain (1 + CS/CL) is usually greater than five, so the AD745, with its higher slew rate and bandwidth is ideally suited to this application. +12V 0.
PAGE 12
AD745 CF R1 CB = CS RB = RS FOR RS >> R1 OR R2 CB = CF || CS RB = R1 || RS CB R1 RB RS AD745 AD745 CS CB CS RS OUTPUT OUTPUT NONINVERTING CONNECTION RB INVERTING CONNECTION C00831–0–3/02(D) R2 Figure 40. Optional External Components for Balancing Source Impedances OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 16-Lead SOIC (R) Package 0.4133 (10.50) 0.3977 (10.00) 9 16 0.2992 (7.60) 0.2914 (7.40) PIN 1 0.4193 (10.65) 0.3937 (10.00) 8 1 0.050 (1.27) BSC 0.0118 (0.30) 0.