Datasheet

AD7490 Data Sheet
Rev. D | Page 22 of 28
SERIAL INTERFACE
Figure 27 shows the detailed timing diagram for serial interfacing
to the AD7490. The serial clock provides the conversion clock
and also controls the transfer of information to and from the
AD7490 during each conversion.
The
CS
signal initiates the data transfer and conversion process.
The falling edge of
CS
puts the track-and-hold into hold mode
and takes the bus out of three-state. The analog input is sampled
at this point. The conversion is also initiated at this point and
requires 16 SCLK cycles to complete. The track-and-hold goes
back into track on the 14
th
SCLK falling edge, as shown in
Figure 27 at point B, except when the write is to the Shadow
register, in which case the track-and-hold does not return to
track until the rising edge of
CS
, that is, Point C in Figure 28.
On the 16
th
SCLK falling edge, the DOUT line goes back into
three-state (assuming the WEAK/
TRI
bit is set to 0). Sixteen
serial clock cycles are required to perform the conversion
process and to access data from the AD7490. The 12 bits of
conversion data are preceded by the four channel address bits,
ADD3 to ADD0, identifying which channel the conversion
result corresponds to.
CS
going low allows the ADD3 address
bit to be read in by the microprocessor or DSP. The remaining
address bits and data bits are then clocked out by subsequent
SCLK falling edges, beginning with the second address bit,
ADD2. Thus, the first SCLK falling edge on the serial clock has
the ADD3 address bit provided and also clocks out address bit
ADD2. The final bit in the data transfer is valid on the 16
th
falling edge, having being clocked out on the previous (15
th
)
falling edge.
Writing information to the control register takes place on the
first 12 falling edges of SCLK in a data transfer, assuming the
MSB, that is, the WRITE bit, has been set to 1. If the control
register is programmed to use the Shadow register, writing
information to the Shadow register takes place on all 16 SCLK
falling edges in the next serial transfer (see Figure 28). The
Shadow register is updated upon the rising edge of
CS
, and the
track-and-hold begins to track the first channel selected in the
sequence.
02691-026
SCLK
DOUT
DIN
CS
WRITE SEQ ADD3 ADD2 ADD1 ADD0 DONTC DONTC DONTC
ADD2 ADD1 ADD0 DB11 DB10 DB2 DB1 DB0
B
t
2
t
3
b
t
3
1 2 3 4 5 6 13 14 15 16
t
9
t
10
t
8
t
4
t
7
t
6
t
5
t
11
t
QUIET
t
CONVERT
THREE-
STATE
THREE-
STATE
ADD3
FOUR IDENTIFICATION BITS
Figure 27. Serial Interface Timing Diagram
02691-027
SCLK
DOUT
DIN
CS
t
2
t
3
t
9
t
10
t
8
t
4
t
7
t
6
t
5
t
11
t
CONVERT
THREE-
STATE
THREE-
STATE
ADD3
FOUR IDENTIFICATION BITS
ADD2 ADD1 ADD0 DB11 DB10 DB2 DB1 DB0
C
1 2 3 4 5 6 13 14 15 16
V
IN
0V
IN
1V
IN
2V
IN
3V
IN
4V
IN
5V
IN
13 V
IN
14 V
IN
15
Figure 28. Writing to Shadow Register Timing Diagram