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AD7564

FEATURES

Four 12-Bit DACs in One Package

4-Quadrant Multiplication

Separate References

Single Supply Operation

Guaranteed Specifications with +3.3 V/+5 V Supply

Low Power

Versatile Serial Interface

Simultaneous Update Capability

Reset Function

28-Pin SOIC, SSOP and DIP Packages

APPLICATIONS

Process Control

Portable Instrumentation

General Purpose Test Equipment

FUNCTIONAL BLOCK DIAGRAM

V A

R B

DAC A

LATCH

INPUT

LATCH A

INPUT

LATCH B

INPUT

LATCH C

INPUT

LATCH D

DAC B

LATCH

DAC C

LATCH

DAC D

LATCH

DAC B

DAC C

DAC D

V B

REF

V D

REF

R D

R C

R A

REF

V C

REF

DGND

LDAC

CLR

AD7564

CONTROL LOGIC

INPUT SHIFT

CLKIN

SDIN

SDOUT

FSIN

I A

I B

I C

I D

OUT1

OUT2

OUT1

OUT2

OUT1

A0 A1

AGND

I C

OUT2

I D

OUT2

PRODUCT HIGHLIGHTS

1. The AD7564 contains four 12-bit current output DACs with

separate V

REF

inputs.

2. The AD7564 can be operated from a single +3.3 V to +5 V

supply.

3. Simultaneous update capability and reset function are

available.

4. The AD7564 features a fast, versatile serial interface com-

patible with modern 3 V and 5 V microprocessors and

microcomputers.

5. Low power, 50 µW at 5 V and 33 µW at 3.3 V.

MOS

+3.3 V/+5 V, Low Power, Quad 12-Bit DAC

One Technology Way, P.O. Box 9106, Norwood. MA 02062-9106, U.S.A.

Tel: Fax:

REV.

Information furnished by Analog Devices is believed to be accurate and

reliable. However, no responsibility is assumed by Analog Devices for its

use, nor for any infringements of patents or other rights of third parties

which may result from its use. No license is granted by implication or

otherwise under any patent or patent rights of Analog Devices.

GENERAL DESCRIPTION

The AD7564 contains four 12-bit DACs in one monolithic

device. The DACs are standard current output with separate

REF

, I

OUT1

, I

OUT2

and R

terminals. These DACs operate from

a single +3.3 V to +5 V supply.

The AD7564 is a serial input device. Data is loaded using

FSIN, CLKIN and SDIN. Two address pins A0 and A1 set up

a device address, and this feature may be used to simplify device

loading in a multi-DAC environment. Alternatively, A0 and A1

can be ignored and the serial out capability used to configure a

daisy-chained system.

All DACs can be simultaneously updated using the asynchro-

nous

LDAC input, and they can be cleared by asserting the

asynchronous

CLR input.

The device is packaged in 28-pin SOIC, SSOP and DIP

packages.

781/329-4700

781/461-3113

Summary of content (17 pages)

PAGE 1
a LC2MOS +3.3 V/+5 V, Low Power, Quad 12-Bit DAC AD7564 FEATURES Four 12-Bit DACs in One Package 4-Quadrant Multiplication Separate References Single Supply Operation Guaranteed Specifications with +3.
PAGE 2
AD7564–SPECIFICATIONS (V = +4.75 V to +5.25 V; I A to I Normal Mode DD OUT1 OUT1D = IOUT2A = IOUT2D = AGND = 0 V; VREF = +10 V; TA = TMIN to TMAX, unless otherwise noted) B Grade1 Units Test Conditions/Comments 12 ± 0.5 ± 0.5 Bits LSB max LSB max 1 LSB = VREF/212 = 2.
PAGE 3
AD7564 Biased Mode1 (VDD = +3 V to +5.5 V; VIOUT1 = VIOUT2 = 1.23 V; AGND = 0 V; VREF = 0 V to 2.45 V; TA = TMIN to TMAX, unless otherwise noted) Parameter A Grade2 Units Test Conditions/Comments ACCURACY Resolution 12 Bits ±1 ± 0.9 1 LSB = (VIOUT2 – VREF)/212 = 300 µV when VIOUT2 = 1.
PAGE 4
AD7564 AC Performance Characteristics Normal Mode (VDD = +4.75 V to +5.25 V; VIOUT1 = VIOUT2 = AGND = 0 V. VREF = 6 V rms, 1 kHz sine wave; DAC output op amp is AD843; TA = TMIN to TMAX, unless otherwise noted. These characteristics are included for Design Guidance and are not subject to test.
PAGE 5
AD7564 Timing Specifications1 (TA = TMIN to TMAX unless otherwise noted) Parameter Limit at Limit at VDD = +3 V to +3.6 V VDD = +4.75 V to +5.
PAGE 6
AD7564 ABSOLUTE MAXIMUM RATINGS 1 (TA = +25°C unless otherwise noted) PIN CONFIGURATION DIP, SOIC and SSOP Packages VDD to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +6 V IOUT1 to DGND . . . . . . . . . . . . . . . . . . . –0.3 V to VDD + 0.3 V IOUT2 to DGND . . . . . . . . . . . . . . . . . . . –0.3 V to VDD + 0.3 V AGND to DGND . . . . . . . . . . . . . . . . . –0.3 V to VDD + 0.3 V Digital Input Voltage to DGND . . . . . . –0.3 V to VDD + 0.3 V VRFB, VREF to DGND . . . . . . . .
PAGE 7
AD7564 PIN DESCRIPTIONS Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 Mnemonic DGND IOUT2C VDD IOUT1C RFBC VREFC IOUT2D IOUT1D RFBD VREFD SDOUT CLR LDAC 14 FSIN 15 SDIN 16 CLKIN 17 A1 18 19 20 21 22 23 24 25 26 27 A0 VREFA RFBA IOUT1A IOUT2A VREFB RFBB IOUT1B N/C AGND 28 IOUT2B REV. B Description Digital Ground. IOUT2 terminal for DAC C. This should normally connect to the signal ground of the system. Positive power supply. This is +5 V ± 5%. IOUT1 terminal for DAC C. Feedback resistor for DAC C.
PAGE 8
AD7564 Output Voltage Settling Time TERMINOLOGY Relative Accuracy This is the amount of time it takes for the output to settle to a specified level for a full-scale input change. For the AD7564, it is specified with the AD843 as the output op amp. Relative accuracy or endpoint linearity is a measure of the maximum deviation from a straight line passing through the endpoints of the DAC transfer function.
PAGE 9
Typical Performance Curves–AD7564 0.5 0.5 NORMAL MODE OF OPERATION VDD = +5V TA = +25°C 0.4 0.4 0.3 0.3 INL – LSBs DNL – LSBs NORMAL MODE OF OPERATION VDD = +5V TA = +25°C 0.2 0.1 0.2 0.1 0.0 0.0 2 4 6 VREF – Volts 8 10 2 Figure 3. Differential Nonlinearity Error vs.
PAGE 10
AD7564 2.0 2.0 VDD = +3.3V TA = +25°C OP AMP = AD820 VREF = +1.23V (AD589) 1.8 1.6 1.6 1.4 DNL – LSBs INL – LSBs 1.4 1.2 1.0 0.8 1.0 0.8 0.6 0.4 0.4 0.2 0.2 0.4 0.6 0.8 1.0 |VREF – VBIAS| – Volts 0.0 0.2 1.4 1.2 Figure 9. Integral Nonlinearity Error vs. VREF (Biased Mode) 0.4 0.6 0.8 1.0 |VREF – VBIAS| – Volts 1.4 1.2 Figure 12. Differential Nonlinearity Error vs. VREF (Biased Mode) 2.0 2.0 VDD = +5V TA = +25°C OP AMP = AD820 VBIAS = +1.23V (AD589) 1.8 1.6 1.6 1.4 DNL – LSBs 1.
PAGE 11
AD7564 Bringing the CLR line low resets the DAC latches to all 0s. The input latches are not affected so that the user can revert to the previous analog output if desired. GENERAL DESCRIPTION D/A Section The AD7564 contains four 12-bit current output D/A converters. A simplified circuit diagram for one of the D/A converters is shown in Figure 15. CLKIN 16-BIT INPUT SHIFT REGISTER FSIN V REF R 2R C 2R B R 2R A R 2R S9 2R S8 2R S0 Figure 16.
PAGE 12
AD7564 BIPOLAR OPERATION 4-Quadrant Multiplication) In the current mode circuit of Figure 19, IOUT2 and hence IOUT1, is biased positive by an amount VBIAS. For the circuit to operate correctly, the DAC ladder termination resistor must be connected internally to IOUT2. This is the case with the AD7564. The output voltage is given by: Figure 18 shows the standard connection diagram for bipolar operation of any one of the DACs in the AD7564. The coding is offset binary as shown in Table IV.
PAGE 13
AD7564 MICROPROCESSOR INTERFACING AD7564 to 80C51 Interface AD7564 to 68HC11 Interface Figure 22 shows a serial interface between the AD7564 and the 68HC11 microcontroller. SCK of the 68HC11 drives SCLK of the AD7564 while the MOSI output drives the serial data line of the AD7564. The FSIN signal is derived from a port line (PC7 shown). A serial interface between the AD7564 and the 80C51 microcontroller is shown in Figure 21.
PAGE 14
AD7564 AD7564 to ADSP-2101/ADSP-2103 Interface Figure 23 shows a serial interface between the AD7564 and the ADSP-2101/ADSP-2103 digital signal processors. The ADSP2101 operates from 5 V while the ADSP-2103 operates from 3 V supplies. These processors are set up to operate in the SPORT Transmit Alternate Framing Mode. AD7564* TMS320C25* +5V CLR The following DSP conditions are recommended: Internal SCLK; Active low Framing Signal; 16-bit word length.
PAGE 15
AD7564 In the circuit of Figure 25: APPLICATIONS Programmable State Variable Filter C1 = C2, R7 = R8, R3 = R4 (i.e., the same code is loaded to each DAC). The AD7564 with its multiplying capability and fast settling time is ideal for many types of signal conditioning applications. The circuit of Figure 25 shows its use in a state variable filter design. This type of filter has three outputs: low pass, high pass and bandpass.
PAGE 16
AD7564 OUTLINE DIMENSIONS 1.565 (39.75) 1.380 (35.05) 28 15 0.580 (14.73) 0.485 (12.31) 1 14 0.625 (15.88) 0.600 (15.24) 0.100 (2.54) BSC 0.250 (6.35) MAX 0.195 (4.95) 0.125 (3.17) 0.015 (0.38) GAUGE PLANE 0.015 (0.38) MIN 0.200 (5.08) 0.115 (2.92) SEATING PLANE 0.022 (0.56) 0.014 (0.36) 0.700 (17.78) MAX 0.005 (0.13) MIN 0.015 (0.38) 0.008 (0.20) 0.070 (1.78) 0.050 (1.
PAGE 17
AD7564 10.50 10.20 9.90 15 28 5.60 5.30 5.00 1 8.20 7.80 7.40 14 0.65 BSC 0.38 0.22 SEATING PLANE 8° 4° 0° COMPLIANT TO JEDEC STANDARDS MO-150-AH 0.95 0.75 0.55 060106-A 0.05 MIN COPLANARITY 0.10 0.25 0.09 1.85 1.75 1.65 2.00 MAX Figure 28.