Datasheet

AD7609 Data Sheet
Rev. A | Page 26 of 36
DIGITAL INTERFACE
The AD7609 provides two interface options: a parallel interface
and a high speed serial interface. The required interface mode is
selected via the
PAR
/SER SEL pin.
The operation of the interface modes is described in the
following sections.
PARALLEL INTERFACE (PAR/SER SEL = 0)
Data can be read from the AD7609 via the parallel data bus with
standard
CS
and
RD
signals. To read the data over the parallel
bus, the
PAR
/SER SEL pin should be tied low. The
CS
and
RD
input signals are internally gated to enable the conversion result
onto the data bus. The data lines, DB15 to DB0, leave their high
impedance state when both
CS
and
RD
are logic low.
The rising edge of the
CS
input signal three-states the bus and
the falling edge of the
CS
input signal takes the bus out of the
high impedance state.
CS
is the control signal that enables the
data lines; it is the function that allows multiple AD7609
devices to share the same parallel data bus. The
CS
signal can
be permanently tied low, and the
RD
signal can be used to
access the conversion results, as shown in
Figure 4. A read
operation of new data can take place after the BUSY signal
goes low (Figure 2), or, alternatively, a read operation of data
from the previous conversion process can take place while
BUSY is high (Figure 3).
The
RD
pin is used to read data from the output conversion
results register. Two
RD
pulses are required to read the full
18-bit conversion result from each channel. Applying a
sequence of 16
RD
pulses to the AD7609
RD
pin clocks the
conversion results out from each channel onto the parallel
output bus, DB[15:0], in ascending order. The first
RD
falling
edge after BUSY goes low clocks out DB[17:2] of the V1 result,
the next
RD
falling edge updates the bus with DB[1:0] of the V1
result. It takes 16
RD
pulses to read the eight 18-bit conversion
results from the AD7609. The 16
th
falling edge of
RD
clocks out
the DB[1:0] conversion result for Channel V8. When the
RD
signal is logic low, it enables the data conversion result from
each channel to be transferred to the digital host (DSP, FPGA).
When there is only one AD7609 in a system/board and it
does not share the parallel bus, data can be read using only one
control signal from the digital host. The
CS
and
RD
signals
can be tied together, as shown in
Figure 5. In this case, the data
bus comes out of three-state on the falling edge of
CS
/
RD
. The
combined
CS
and
RD
signal allows the data to be clocked out
of the
AD7609 and to be read by the digital host. In this case,
CS
is used to frame the data transfer of each data channel and
16
CS
pulses are required to read the eight channels of data.
AD7609
14
BUSY
12
RD
33:16
DB[15:0]
13
CS
DIGITAL
HOST
INTERRUPT
09760-040
Figure 43. AD7609 Interface Diagram: One AD7609 Using the Parallel Bus;
CS
and
RD
Shorted Together
SERIAL INTERFACE (PAR/SER SEL = 1)
To read data back from the AD7609 over the serial interface,
the
PAR
/SER SEL pin should be tied high. The
CS
and SCLK
signals are used to transfer data from the AD7609. The
AD7609
has two serial data output pins, D
OUT
A and D
OUT
B. Data can be
read back from the AD7609 using one or both of these D
OUT
lines. For the AD7609, conversion results from Channel V1 to
Channel V4 first appear on D
OUT
A, whereas conversion results
from Channel V5 to Channel V8 first appear on D
OUT
B.
The
CS
falling edge takes the data output lines (D
OUT
A and
D
OUT
B) out of three-state and clocks out the MSB of the conver-
sion result. The rising edge of SCLK clocks all subsequent data
bits onto the serial data outputs, D
OUT
A and D
OUT
B. The
CS
input can be held low for the entire serial read or it can be
pulsed to frame each channel read of 18 SCLK cycles.
Figure 44 shows a read of eight simultaneous conversion results
using two D
OUT
lines on the AD7609. In this case, a 72 SCLK
transfer is used to access data from the AD7609 and
CS
is held
low to frame the entire 72 SCLK cycles. Data can also be clocked
out using only one D
OUT
line, in which case D
OUT
A is recom-
mended to access all conversion data, because the channel data
is output in ascending order. For the AD7609 to access all eight
conversion results on one D
OUT
line, a total of 144 SCLK cycles
are required. These 144 SCLK cycles can be framed by one
CS
signal or each group of 18 SCLK cycles can be individually
framed by the
CS
signal. The disadvantage of using only one
D
OUT
line is that the throughput rate is reduced if reading after
conversion. The unused D
OUT
line should be left unconnected
in serial mode. For the AD7609, if D
OUT
B is to be used as a
single D
OUT
line, the channel results are output in the following
order: V5, V6, V7, V8, V1, V2, V3, V4; however, the FRSTDATA
indicator returns low after V5 is read on D
OUT
B.