Datasheet

Data Sheet AD7609
Rev. A | Page 9 of 36
Limit at T
MIN
, T
MAX
Parameter Min Typ Max Unit Description
t
27
Delay from
RD falling edge to FRSTDATA low
22 ns V
DRIVE
= 3.3 V to 5.25 V
29 ns V
DRIVE
= 2.3 V to 2.7 V
t
28
Delay from 18
th
SCLK falling edge to FRSTDATA low
20 ns V
DRIVE
= 3.3 V to 5.25 V
27 ns V
DRIVE
= 2.3 V to 2.7 V
t
29
29 ns
Delay from
CS rising edge until FRSTDATA three-state enabled
1
Sample tested during initial release to ensure compliance. All input signals are specified with t
R
= t
F
= 5 ns (30% to 70% of V
DD
) and timed from a voltage level of 1.6 V.
2
The delay between the CONVST x signals was measured as the maximum time allowed while ensuring a <40 LSB performance matching between channel sets.
3
A buffer is used on the data output pins for these measurements, which is equivalent to a load of 20 pF on the output pins.
Timing Diagrams
t
CYCLE
t
3
t
5
t
2
t
4
t
1
t
7
t
RESET
t
CONV
CONVST A/
CONVST B
CONVST A/
CONVST B
BUSY
CS
RESET
09760-002
Figure 2. CONVST x Timing—Reading After a Conversion
t
CYCLE
t
3
t
5
t
6
t
2
t
1
t
CONV
CONVST A/
CONVST B
CONVST A/
CONVST B
BUSY
CS
t
7
t
RESET
RESET
09760-003
Figure 3. CONVST x Timing—Reading During a Conversion
DATA:
DB[15:0]
FRSTDATA
CS
RD
INVALID
V1
[17:2]
V1
[1:0]
V2
[17:2]
V8
[17:2]
V8
[1:0]
V2
[1:0]
t
10
t
8
t
13
t
24
t
26
t
27
t
14
t
11
t
9
t
16
t
17
t
29
t
15
09760-004
Figure 4. Parallel Mode Separate
CS
and
RD
Pulses