Datasheet

AD7654
Rev. B | Page 18 of 28
SAMPLING RATE (kSPS)
0.1
POWER DISSIP
A
TION (mW)
100 1000
1
10
100
1000
NORMAL
IMPULSE
03057-021
101
Figure 21. Power Dissipation vs. Sample Rate
CONVERSION CONTROL
Figure 22 shows the detailed timing diagrams of the
conversion
process. The AD7654 is controlled by the signal
CNVST
, which initiates conversion. Once initiated, it cannot be
restarted or aborted, even by the power-down input, PD, until
the conversion is complete. The
CNVST
signal operates
independently of the
CS
and
RD
signals.
BUSY
ACQUIRE
t
2
t
1
t
3
t
4
t
5
t
6
t
7
t
8
CONVERT A
ACQUIRE
CONVERT
CONVERT B
t
12
A0
t
14
t
15
t
13
t
11
t
10
EOC
CNVST
03057-022
MODE
Figure 22. Basic Conversion Timing
Although
CNVST
is a digital signal, it should be designed with
special care with fast, clean edges and levels, and with minimum
overshoot and undershoot or ringing.
For applications where the SNR is critical, the
CNVST
signal
should have very low jitter. Some solutions to achieve this are to
use a dedicated oscillator for
CNVST
generation or, at least, to
clock it with a high frequency, low jitter clock, as shown in
Figure 18.
In impulse mode, conversions can be automatically initiated. If
CNVST
is held low when BUSY is low, the AD7654 controls the
acquisition phase and automatically initiates a new conversion.
By keeping
CNVST
low, the AD7654 keeps the conversion
process running by itself. Note that the analog input has to be
settled when BUSY goes low. Also, at power-up,
CNVST
should
be brought low once to initiate the conversion process. In this
mode, the AD7654 could sometimes run slightly faster than the
guaranteed limits of 444 kSPS in impulse mode. This feature
does not exist in normal mode.
DIGITAL INTERFACE
The AD7654 has a versatile digital interface; it can be interfaced
with the host system by using either a serial or parallel interface.
The serial interface is multiplexed on the parallel data bus. The
AD7654 digital interface accommodates either 3 V or 5 V logic
by simply connecting the OVDD supply pin of the AD7654 to
the host system interface digital supply.
The two signals
CS
and
RD
control the interface. When at least
one of these signals is high, the interface outputs are in high
impedance. Usually,
CS
allows the selection of each AD7654
in multicircuit applications and is held low in a single
AD7654
design.
RD
is generally used to enable the conversion result on
the data bus. In parallel mode, signal A/
B
allows the choice of
reading either the output of Channel A or Channel B, whereas
in serial mode, signal A/
B
controls which channel is output first.
Figure 23 details the timing when using the RESET input. Note
the current conversion, if any, is aborted and the data bus is
high impedance while RESET is high.
t
9
RESET
DATA
BUS
BUSY
t
8
CNVST
03057-023
Figure 23. Reset Timing
PARALLEL INTERFACE
The AD7654 is configured to use the parallel interface when
SER/
PAR
is held low.
Master Parallel Interface
Data can be read continuously by tying
CS
and
RD
low, thus
requiring minimal microprocessor connections. However, in
this mode, the data bus is always driven and cannot be used in
shared bus applications (unless the device is held in RESET).
Figure 24 details the timing for this mode.