Datasheet

ManualsBrandsANALOG DEVICES ManualsData collecting ICsData acquisition IC - AD converter (ADC) External MSOP 10

16-Bit, 250 kSPS PulSAR

ADC in MSOP/QFN

AD7685

Rev. C

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FEATURES

16-bit resolution with no missing codes

Throughput: 250 kSPS

INL: ±0.6 LSB typical, ±2 LSB maximum (±0.003% of FSR)

SINAD: 93.5 dB @ 20 kHz

THD: −110 dB @ 20 kHz

Pseudo differential analog input range

0 V to V

REF

with V

REF

up to VDD

No pipeline delay

Single-supply operation 2.3 V to 5.5 V with

1.8 V to 5 V logic interface

Serial interface SPI®-/QSPI™-/MICROWIRE™-/DSP-compatible

Daisy-chain multiple ADCs, BUSY indicator

Power dissipation

1.4 μW @ 2.5 V/100 SPS

1.35 mW @ 2.5 V/100 kSPS, 4 mW @ 5 V/100 kSPS

Standby current: 1 nA

10-lead package: MSOP (MSOP-8 size) and

3 mm × 3 mm QFN (LFCSP) (SOT-23 size)

Pin-for-pin-compatible with 10-lead MSOP/QFN PulSAR® ADCs

APPLICATIONS

Battery-powered equipment

Medical instruments

Mobile communications

Personal digital assistants (PDAs)

Data acquisition

Instrumentation

Process controls

02968-005

CODE

655360 16384 32768 49152

INL (LSB)

2.0

1.5

1.0

0.5

–0.5

–1.0

–1.5

–2.0

POSITIVE INL = +0.33LSB

NEGATIVE INL = –0.50LSB

Figure 1. Integral Nonlinearity vs. Code.

APPLICATION DIAGRAM

AD7685

REF

GND

VDD

IN+

IN–

VIO

SDI

SCK

SDO

CNV

1.8V TO VDD

3- OR 4-WIRE INTERFACE

(SPI, DAISY CHAIN, CS)

0.5

TO VDD 2.5

TO 5V

0 TO VREF

02968-001

Figure 2.

Table 1. MSOP, QFN (LFCSP)/SOT-23

14-/16-/18-Bit PulSAR ADC

Type

100

kSPS

250

kSPS

400 kSPS

500 kSPS

1000

kSPS

ADC

Driver

18-Bit True AD7691 AD7690 AD7982 ADA4941

Differential AD7982 ADA4841

16-Bit True AD7684 AD7687 AD7688 ADA4941

Differential AD7693 ADA4841

16-Bit Pseudo AD7680 AD7685 AD7686 AD7980 ADA4841

Differential AD7683 AD7694

14-Bit Pseudo AD7940 AD7942 AD7946 ADA4841

Differential

GENERAL DESCRIPTION

The AD7685 is a 16-bit, charge redistribution successive

approximation, analog-to-digital converter (ADC) that operates

from a single power supply, VDD, between 2.3 V to 5.5 V. It

contains a low power, high speed, 16-bit sampling ADC with no

missing codes, an internal conversion clock, and a versatile serial

interface port. The part also contains a low noise, wide bandwidth,

short aperture delay, track-and-hold circuit. On the CNV rising

edge, it samples an analog input IN+ between 0 V to REF with

respect to a ground sense IN−. The reference voltage, REF, is

applied externally and can be set up to the supply voltage.

Power dissipation scales linearly with throughput.

The SPI-compatible serial interface also features the ability,

using the SDI input, to daisy chain several ADCs on a single

3-wire bus or provides an optional BUSY indicator. It is

compatible with 1.8 V, 2.5 V, 3 V, or 5 V logic using the

separate supply VIO.

The AD7685 is housed in a 10-lead MSOP or a 10-lead QFN

(LFCSP) with operation specified from −40°C to +85°C.

Summary of content (28 pages)

PAGE 1
6-Bit, 250 kSPS PulSAR ADC in MSOP/QFN AD7685 FEATURES APPLICATION DIAGRAM APPLICATIONS 0.5 INL (LSB) IN– REF VDD VIO SDI AD7685 1.8V TO VDD SCK 3- OR 4-WIRE INTERFACE (SPI, DAISY CHAIN, CS) SDO GND CNV Figure 2. Table 1.
PAGE 2
AD7685 TABLE OF CONTENTS Features .............................................................................................. 1 Driver Amplifier Choice ........................................................... 16 Applications....................................................................................... 1 Voltage Reference Input ............................................................ 16 Application Diagram........................................................................
PAGE 3
AD7685 SPECIFICATIONS VDD = 2.3 V to 5.5 V, VIO = 2.3 V to VDD, VREF = VDD, TA = –40°C to +85°C, unless otherwise noted. Table 2.
PAGE 4
AD7685 VDD = 2.3 V to 5.5 V, VIO = 2.3 V to VDD, VREF = VDD, TA = –40°C to +85°C, unless otherwise noted. Table 3. Parameter REFERENCE Voltage Range Load Current SAMPLING DYNAMICS −3 dB Input Bandwidth Aperture Delay DIGITAL INPUTS Logic Levels VIL VIH IIL IIH DIGITAL OUTPUTS Data Format Pipeline Delay Conditions VOL VOH POWER SUPPLIES VDD VIO VIO Range Standby Current 1, 2 Power Dissipation ISINK = +500 μA ISOURCE = −500 μA TEMPERATURE RANGE 3 Specified Performance Min Typ 0.5 Max Unit VDD + 0.
PAGE 5
AD7685 TIMING SPECIFICATIONS −40°C to +85°C, VIO = 2.3 V to 5.5 V or VDD + 0.3 V, whichever is the lowest, unless otherwise stated. Table 4. VDD = 4.5 V to 5.5 V 1 Parameter Conversion Time: CNV Rising Edge To Data Available Acquisition Time Time Between Conversions CNV Pulse Width (CS Mode) SCK Period (CS Mode) SCK Period (Chain Mode) VIO Above 4.5 V VIO Above 3 V VIO Above 2.7 V VIO Above 2.
PAGE 6
AD7685 −40°C to +85°C, VIO = 2.3 V to 4.5 V or VDD + 0.3 V, whichever is the lowest, unless otherwise stated. Table 5. VDD = 2.3V to 4.5 V 1 Parameter Conversion Time: CNV Rising Edge to Data Available Acquisition Time Time Between Conversions CNV Pulse Width (CS Mode) SCK Period (CS Mode) SCK Period (Chain Mode) VIO Above 3 V VIO Above 2.7 V VIO Above 2.3 V SCK Low Time SCK High Time SCK Falling Edge to Data Remains Valid SCK Falling Edge to Data Valid Delay VIO Above 3 V VIO Above 2.7 V VIO Above 2.
PAGE 7
AD7685 ABSOLUTE MAXIMUM RATINGS Table 6. Parameter Analog Inputs IN+ 1 , IN−1, REF Supply Voltages VDD, VIO to GND VDD to VIO Digital Inputs to GND Digital Outputs to GND Storage Temperature Range Junction Temperature θJA Thermal Impedance θJC Thermal Impedance Lead Temperature Vapor Phase (60 sec) Infrared (15 sec) 1 Rating GND − 0.3 V to VDD + 0.3 V or ±130 mA −0.3 V to +7 V ±7 V −0.3 V to VIO + 0.3 V −0.3 V to VIO + 0.
PAGE 8
AD7685 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS REF 1 IN+ 3 10 VIO AD7685 9 SDI TOP VIEW (Not to Scale) 8 SCK 7 SDO 6 CNV IN+ 3 IN– 4 GND 5 GND 5 AD7685 9 SDI TOP VIEW (Not to Scale) 8 SCK 7 SDO 6 CNV NOTES 1. EXPOSED PAD CONNECTED TO GND. THIS CONNECTION IS NOT REQUIRED TO MEET THE ELECTRICAL PERFORMANCES. 02968-004 REF 1 VDD 2 IN– 4 10 VIO Figure 5. 10-Lead MSOP Pin Configuration 02968-005 VDD 2 Figure 6. 10-Lead QFN (LFCSP) Pin Configuration Table 7.
PAGE 9
AD7685 TERMINOLOGY Integral Nonlinearity Error (INL) INL refers to the deviation of each individual code from a line drawn from negative full scale through positive full scale. The point used as negative full scale occurs ½ LSB before the first code transition. Positive full scale is defined as a level 1½ LSB beyond the last code transition. The deviation is measured from the middle of each code to the true straight line (see Figure 26).
PAGE 10
AD7685 TYPICAL PERFORMANCE CHARACTERISTICS 1.5 1.0 0.5 0.5 DNL (LSB) 1.0 0 –0.5 0 –0.5 –1.0 –1.0 –1.5 –1.5 –2.0 0 16384 32768 CODE 49152 65536 POSITIVE DNL = +0.21LSB NEGATIVE DNL = –0.30LSB 1.5 –2.0 02968-047 INL (LSB) 2.0 POSITIVE INL = +0.33LSB NEGATIVE INL = –0.50LSB 0 16384 Figure 7. Integral Nonlinearity vs. Code 250000 32768 CODE 49152 65536 02968-008 2.0 Figure 10. Differential Nonlinearity vs. Code 140000 VDD = REF = 5V VDD = REF = 2.
PAGE 11
AD7685 100 –90 17 –95 SNR –100 16 90 ENOB 15 THD, SFDR (dB) SINAD ENOB (Bits) SINAD (dB) 95 14 85 –105 –110 THD –115 SFDR –120 2.7 3.1 3.5 3.9 4.3 4.7 REFERENCE VOLTAGE (V) 5.1 13 5.5 –130 2.3 02968-011 80 2.3 Figure 13. SNR, SINAD, and ENOB vs. Reference Voltage 3.1 3.5 3.9 4.3 4.7 REFERENCE VOLTAGE (V) 5.1 5.5 Figure 16. THD, SFDR vs. Reference Voltage 100 –60 95 –70 VREF = 5V, –10dB VREF = 5V, –1dB 90 –80 VREF = 5V, –1dB THD (dB) SINAD (dB) 2.
PAGE 12
AD7685 1000 –105 fS = 100kSPS VDD = 5V OPERATING CURRENTS (µA) 94 SNR –110 92 THD (dB) 93 THD –115 91 750 VDD = 2.5V 500 250 –8 –6 –4 INPUT LEVEL (dB) –2 0 –120 0 –55 Figure 19. SNR and THD vs. Input Level –35 –15 5 25 45 65 TEMPERATURE (°C) 85 105 125 02968-020 VIO 90 –10 02968-017 SNR REFERENCE TO FULL SCALE (dB) 95 Figure 22. Operating Currents vs. Temperature 6 1000 5 fS = 100kSPS OFFSET, GAIN ERROR (LSB) 750 VDD 500 250 3.
PAGE 13
AD7685 THEORY OF OPERATION IN+ SWITCHES CONTROL MSB 32,768C 16,384C LSB 4C 2C C SW+ C BUSY REF COMP GND 32,768C 16,384C 4C 2C C MSB CONTROL LOGIC OUTPUT CODE C LSB SW– 02968-023 CNV IN– Figure 25. ADC Simplified Schematic CIRCUIT INFORMATION CONVERTER OPERATION The AD7685 is a fast, low power, single-supply, precise 16-bit ADC using a successive approximation architecture. The AD7685 is a successive approximation ADC based on a charge redistribution DAC.
PAGE 14
AD7685 TYPICAL CONNECTION DIAGRAM The ideal transfer characteristic for the AD7685 is shown in Figure 26 and Table 8. Figure 27 shows an example of the recommended connection diagram for the AD7685 when multiple supplies are available. ADC CODE (STRAIGHT BINARY) Transfer Functions 111...111 111...110 111...101 000...010 000...001 –FS + 1 LSB +FS – 1 LSB +FS – 1.5 LSB –FS + 0.5 LSB 02968-024 000...000 –FS ANALOG INPUT Figure 26. ADC Ideal Transfer Function ≥7V REF1 5V 10µF2 100nF 1.
PAGE 15
AD7685 ANALOG INPUTS Figure 28 shows an equivalent circuit of the input structure of the AD7685. The two diodes, D1 and D2, provide ESD protection for the analog inputs IN+ and IN−. Care must be taken to ensure that the analog input signal never exceeds the supply rails by more than 0.3 V because this will cause these diodes to begin to forward-bias and start conducting current. These diodes can handle a forward-biased current of 130 mA maximum.
PAGE 16
AD7685 DRIVER AMPLIFIER CHOICE VOLTAGE REFERENCE INPUT Although the AD7685 is easy to drive, the driver amplifier needs to meet the following requirements: The AD7685 voltage reference input, REF, has a dynamic input impedance and should therefore be driven by a low impedance source with efficient decoupling between the REF and GND pins, as explained in the Layout section.
PAGE 17
AD7685 The AD7685 powers down automatically at the end of each conversion phase and, therefore, the power scales linearly with the sampling rate, as shown in Figure 32. This makes the part ideal for low sampling rate (even a few Hz) and low batterypowered applications. 10000 OPERATING CURRENTS (µA) 1000 VDD = 5V VDD = 2.5V 100 10 1 VIO 0.1 1000 10000 SAMPLING RATE (SPS) 100000 02968-030 100 1000000 Figure 32. Operating Currents vs.
PAGE 18
AD7685 valid on both SCK edges. Although the rising edge can be used to capture the data, a digital host using the SCK falling edge will allow a faster reading rate provided it has an acceptable hold time. After the 16th SCK falling edge or when CNV goes high, whichever is earlier, SDO returns to high impedance. CS MODE 3-WIRE, NO BUSY INDICATOR This mode is usually used when a single AD7685 is connected to an SPI-compatible digital host.
PAGE 19
AD7685 powers down. The data bits are then clocked out, MSB first, by subsequent SCK falling edges. The data is valid on both SCK edges. Although the rising edge can be used to capture the data, a digital host using the SCK falling edge will allow a faster reading rate provided it has an acceptable hold time. After the optional 17th SCK falling edge, or when CNV goes high, whichever is earlier, SDO returns to high impedance.
PAGE 20
AD7685 conversion is complete, the AD7685 enters the acquisition phase and powers down. Each ADC result can be read by bringing low its SDI input, which consequently outputs the MSB onto SDO. The remaining data bits are then clocked by subsequent SCK falling edges. The data is valid on both SCK edges. Although the rising edge can be used to capture the data, a digital host using the SCK falling edge will allow a faster reading rate, provided it has an acceptable hold time.
PAGE 21
AD7685 as an interrupt signal to initiate the data readback controlled by the digital host. The AD7685 then enters the acquisition phase and powers down. The data bits are then clocked out, MSB first, by subsequent SCK falling edges. The data is valid on both SCK edges. Although the rising edge can be used to capture the data, a digital host using the SCK falling edge will allow a faster reading rate provided it has an acceptable hold time.
PAGE 22
AD7685 AD7685 enters the acquisition phase and powers down. The remaining data bits stored in the internal shift register are then clocked by subsequent SCK falling edges. For each ADC, SDI feeds the input of the internal shift register and is clocked by the SCK falling edge. Each ADC in the chain outputs its data MSB first, and 16 × N clocks are required to readback the N ADCs. The data is valid on both SCK edges.
PAGE 23
AD7685 Figure 44) SDO is driven high. This transition on SDO can be used as a BUSY indicator to trigger the data readback controlled by the digital host. The AD7685 then enters the acquisition phase and powers down. The data bits stored in the internal shift register are then clocked out, MSB first, by subsequent SCK falling edges. For each ADC, SDI feeds the input of the internal shift register and is clocked by the SCK falling edge.
PAGE 24
AD7685 APPLICATION HINTS LAYOUT The printed circuit board (PCB) that houses the AD7685 should be designed so that the analog and digital sections are separated and confined to certain areas of the board. The pinout of the AD7685 with all its analog signals on the left side and all its digital signals on the right side eases this task. Avoid running digital lines under the device because these couple noise onto the die, unless a ground plane under the AD7685 is used as a shield.
PAGE 25
AD7685 TRUE 16-BIT ISOLATED APPLICATION EXAMPLE In applications where high accuracy and isolation are required, for example, power monitoring, motor control, and some medical equipment, the circuit given in Figure 48, using the AD7685 and the ADuM1402C digital isolator, provides a compact and high performance solution. Multiple AD7685s are daisy-chained to reduce the number of signals to isolate. Note that the SCKOUT, which is a readback of the AD7685’s clock, has a very short skew with the DATA signal.
PAGE 26
AD7685 OUTLINE DIMENSIONS 3.10 3.00 2.90 10 3.10 3.00 2.90 1 5.15 4.90 4.65 6 5 PIN 1 IDENTIFIER 0.50 BSC 0.95 0.85 0.75 15° MAX 1.10 MAX 0.30 0.15 0.70 0.55 0.40 0.23 0.13 6° 0° 091709-A 0.15 0.05 COPLANARITY 0.10 COMPLIANT TO JEDEC STANDARDS MO-187-BA Figure 49.10-Lead Micro Small Outline Package [MSOP] (RM-10) Dimensions shown in millimeters 2.48 2.38 2.23 3.10 3.00 SQ 2.90 0.50 BSC 6 0.50 0.40 0.30 5 TOP VIEW 0.80 0.75 0.70 SEATING PLANE 10 1.74 1.64 1.49 EXPOSED PAD 0.
PAGE 27
AD7685 ORDERING GUIDE Integral Nonlinearity ±6 LSB max No Missing Code 15 Bits Temperature Range –40°C to +85°C AD7685ACPZRL7 ±6 LSB max 15 Bits –40°C to +85°C AD7685ARMZ AD7685ARMZRL7 ±6 LSB max ±6 LSB max 15 Bits 15 Bits –40°C to +85°C –40°C to +85°C AD7685BCPZRL ±3 LSB max 16 Bits –40°C to +85°C AD7685BCPZRL7 ±3 LSB max 16 Bits –40°C to +85°C AD7685BRMZ AD7685BRMZRL7 ±3 LSB max ±3 LSB max 16 Bits 16 Bits –40°C to +85°C –40°C to +85°C AD7685CCPZRL ±2 LSB max 16 Bits –40°C to +85°