Datasheet

ManualsBrandsANALOG DEVICES ManualsData collecting ICsData acquisition IC - AD converter (ADC) External MSOP 10

18-Bit, 1.5 LSB INL, 250 kSPS PulSAR

Differential ADC in MSOP/QFN

Data Sheet

AD7691

Rev. C

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700 www.analog.com

FEATURES

18-bit resolution with no missing codes

Throughput: 250 kSPS

INL: ±0.75 LSB typical, ±1.5 LSB maximum (±6 ppm of FSR)

Dynamic range: 102 dB typical @ 250 kSPS

Oversampled dynamic range: 125 dB @1 kSPS

Noise-free code resolution: 20 bits @ 1 kSPS

Effective resolution: 22.7 bits @ 1 kSPS

SINAD: 101.5 dB typical @ 1 kHz

THD: −125 dB typical @ 1 kHz

True differential analog input range: ±V

REF

0 V to V

REF

with V

REF

up to VDD on both inputs

No pipeline delay

Single-supply 2.3 V to 5 V operation with

1.8 V/2.5 V/3 V/5 V logic interface

Serial interface SPI-/QSPI™-/MICROWIRE™-/DSP-compatible

Ability to daisy-chain multiple ADCs

Optional busy indicator feature

Power dissipation

1.35 mW @ 2.5 V/100 kSPS, 4 mW @ 5 V/100 kSPS

1.4 μW @ 2.5 V/100 SPS

Standby current: 1 nA

10-lead packages: MSOP (MSOP-8 size) and

3 mm × 3 mm QFN (LFCSP) (SOT-23 size)

Pin-for-pin compatible with the18-bit AD7690 and

16-bit AD7693, AD7688, and AD7687

APPLICATIONS

Battery-powered equipment

Data acquisitions

Seismic data acquisition systems

Instrumentation

Medical instruments

1.5

–1.5

0 262144

CODE

INL (LSB)

1.0

0.5

–0.5

–1.0

65536 131072 196608

POSITIVE INL = 0.43LSB

NEGATIVE INL = –0.62LSB

06146-025

Figure 1. Integral Nonlinearity vs. Code, 5 V

APPLICATION DIAGRAM

AD7691

REF

GND

VDD

IN+

IN–

VIO

SDI

SCK

SDO

CNV

+1.8V TO VDD

3- OR 4-WIRE

INTERFACE

(SPI, DAISY CHAIN, CS)

+0.5V TO VDD

±10V, ±5V, ...

+2.5V TO +5

ADA4941

6146-001

Figure 2.

Table 1. MSOP, QFN (LFCSP)/SOT-23

14-/16-/18-Bit PulSAR® ADC

Type

100

kSPS

250

kSPS

400 kSPS to

500 kSPS

≥1000

kSPS

ADC

Driver

18-Bit True

Differential

AD7691 AD7690

AD7982

AD7984

ADA4941-1

ADA4841-x

16-Bit True

Differential

AD7684 AD7687 AD7688

AD7693

ADA4941-1

ADA4841-x

16-Bit

Pseudo

Differential

AD7680

AD7683

AD7685

AD7694

AD7686 AD7980 ADA4841-x

14-Bit

Pseudo

Differential

AD7940 AD7942 AD7946 ADA4841-1

GENERAL DESCRIPTION

The AD7691 is an 18-bit, charge redistribution, successive

approximation, analog-to-digital converter (ADC) that operates

from a single power supply, VDD, between 2.3 V and 5 V. It

contains a low power, high speed, 18-bit sampling ADC with no

missing codes, an internal conversion clock, and a versatile

serial interface port. On the CNV rising edge, it samples the

voltage difference between the IN+ and IN− pins. The voltages

on these pins swing in opposite phases between 0 V and REF.

The reference voltage, REF, is applied externally and can be set

up to the supply voltage.

The part’s power scales linearly with throughput.

The SPI-compatible serial interface also features the ability,

using the SDI input, to daisy-chain several ADCs on a single

3-wire bus and provides an optional busy indicator. It is compatible

with 1.8 V, 2.5 V, 3 V, or 5 V logic, using the separate VIO supply.

The AD7691 is housed in a 10-lead MSOP or a 10-lead QFN

(LFCSP) with operation specified from −40°C to +85°C.

Summary of content (28 pages)

PAGE 1
8-Bit, 1.5 LSB INL, 250 kSPS PulSAR Differential ADC in MSOP/QFN AD7691 Data Sheet APPLICATION DIAGRAM 18-bit resolution with no missing codes Throughput: 250 kSPS INL: ±0.75 LSB typical, ±1.5 LSB maximum (±6 ppm of FSR) Dynamic range: 102 dB typical @ 250 kSPS Oversampled dynamic range: 125 dB @1 kSPS Noise-free code resolution: 20 bits @ 1 kSPS Effective resolution: 22.7 bits @ 1 kSPS SINAD: 101.
PAGE 2
AD7691 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Driver Amplifier Choice ........................................................... 16 Applications....................................................................................... 1 Single-to-Differential Driver .................................................... 16 Application Diagram......................................................................
PAGE 3
Data Sheet AD7691 SPECIFICATIONS VDD = 2.3 V to 5.25 V, VIO = 2.3 V to VDD, VREF = VDD, all specifications TMIN to TMAX, unless otherwise noted. Table 2.
PAGE 4
AD7691 Data Sheet VDD = 2.3 V to 5.25 V, VIO = 2.3 V to VDD, VREF = VDD, all specifications TMIN to TMAX, unless otherwise noted. Table 3. Parameter REFERENCE Voltage Range Load Current SAMPLING DYNAMICS −3 dB Input Bandwidth Aperture Delay DIGITAL INPUTS Logic Levels VIL VIH IIL IIH DIGITAL OUTPUTS Data Format Pipeline Delay 1 VOL VOH POWER SUPPLIES VDD VIO VIO Range Standby Current 2, 3 Power Dissipation Energy per Conversion TEMPERATURE RANGE 4 Specified Performance Conditions/Comments Min Typ 0.
PAGE 5
Data Sheet AD7691 TIMING SPECIFICATIONS VDD = 4.5 V to 5.25 V, VIO = 2.3 V to VDD, VREF = VDD, all specifications TMIN to TMAX, unless otherwise noted. 1 Table 4. Parameter Conversion Time: CNV Rising Edge to Data Available Acquisition Time Time Between Conversions CNV Pulse Width (CS Mode) SCK Period (CS Mode) SCK Period (Chain Mode) VIO Above 4.5 V VIO Above 3 V VIO Above 2.7 V VIO Above 2.
PAGE 6
AD7691 Data Sheet VDD = 2.3 V to 4.5 V, VIO = 2.3 V to VDD, VREF = VDD, all specifications TMIN to TMAX, unless otherwise noted. 1 Table 5. Parameter Conversion Time: CNV Rising Edge to Data Available Acquisition Time Time Between Conversions CNV Pulse Width (CS Mode) SCK Period (CS Mode) SCK Period (Chain Mode) VIO Above 3 V VIO Above 2.7 V VIO Above 2.3 V SCK Low Time SCK High Time SCK Falling Edge to Data Remains Valid SCK Falling Edge to Data Valid Delay VIO Above 3 V VIO Above 2.7 V VIO Above 2.
PAGE 7
Data Sheet AD7691 ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 6. Parameter Analog Inputs (IN+, IN−)1 REF Supply Voltages VDD, VIO to GND VDD to VIO Digital Inputs to GND Digital Outputs to GND Storage Temperature Range Junction Temperature Lead Temperature Range 1 θJA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Rating GND − 0.3 V to VDD + 0.3 V or ±130 mA GND − 0.3 V to VDD + 0.3 V Table 7.
PAGE 8
AD7691 Data Sheet PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS REF 1 IN+ 3 10 VIO AD7691 9 SDI TOP VIEW (Not to Scale) 8 SCK 7 SDO 6 CNV VDD 2 IN+ 3 IN– 4 GND 5 GND 5 AD7691 TOP VIEW (Not to Scale) 9 SDI 8 SCK 7 SDO 6 CNV NOTES 1. THE EXPOSED PAD IS NOT CONNECTED INTERNALLY. FOR INCREASED RELIABILITY OF THE SOLDER JOINTS, IT IS RECOMMENDED THAT THE PAD BE SOLDERED TO THE GROUND PLANE. 06146-004 REF 1 IN– 4 10 VIO Figure 5.
PAGE 9
Data Sheet AD7691 TYPICAL PERFORMANCE CHARACTERISTICS 1.0 1.5 POSITIVE DNL = 0.37LSB NEGATIVE DNL = –0.33LSB POSITIVE INL = 0.39LSB NEGATIVE INL = –0.73LSB 1.0 0.5 DNL (LSB) INL (LSB) 0.5 0 0 –0.5 –0.5 65536 0 131072 196608 –1.
PAGE 10
AD7691 Data Sheet 104 18 SNR –105 102 –110 17 SINAD 16 94 ENOB (Bits) ENOB 96 THD, SFDR (dB) 98 92 –115 THD –120 –125 15 90 –130 88 2.9 3.2 3.5 3.8 4.1 4.4 4.7 5.0 14 5.3 –135 2.3 06146-032 2.6 REFERENCE VOLTAGE (V) 2.6 2.9 3.2 3.5 3.8 4.1 4.4 4.7 5.0 5.3 105 125 REFERENCE VOLTAGE (V) Figure 13. SNR, SINAD, and ENOB vs. Reference Voltage 06146-038 SFDR 86 2.3 Figure 16. THD, SFDR vs.
PAGE 11
Data Sheet AD7691 –90 SNR 5V GAIN ERROR –95 SNR 2.5V 99 4 OFFSET, GAIN ERROR (LSB) 102 –100 –110 93 THD 5V 90 –115 87 –120 THD 2.5V 81 –10 –8 –6 –4 0 –2 2 0 –2 –4 –125 OFFSET ERROR –130 –6 –55 06146-041 84 THD (dB) –105 96 INPUT LEVEL (dB) –15 25 45 65 85 105 125 Figure 22. Zero Error, Gain Error vs. Temperature 1000 1000 fS =100kSPS POWER-DOWN CURRENT (nA) VDD = 5V 750 VDD = 2.
PAGE 12
AD7691 Data Sheet 95 90 VREF = VDD = 5V 85 90 80 75 CMRR (dB) 80 75 70 65 60 55 50 70 1 10 100 1000 FREQUENCY (kHz) 10000 Figure 25. PSSR vs. Frequency 40 1 10 100 1000 FREQUENCY (kHz) Figure 26. Analog Input CMRR vs. Frequency Rev.
PAGE 13
Data Sheet AD7691 TERMINOLOGY Least Significant Bit (LSB) The least significant bit, or LSB, is the smallest increment that can be represented by a converter. For an analog-to-digital converter with N bits of resolution, the LSB expressed in volts is LSB(V) = Noise-Free Code Resolution It is the number of bits beyond which it is impossible to resolve individual codes distinctly. It is calculated as Noise-Free Code Resolution = log2(2N/Peak-to-Peak Noise) and is expressed in bits.
PAGE 14
AD7691 Data Sheet THEORY OF OPERATION IN+ SWITCHES CONTROL MSB REF 131,072C 65,536C LSB 4C 2C C SW+ C BUSY COMP GND 131,072C 65,536C 4C 2C C CONTROL LOGIC OUTPUT CODE C MSB LSB SW– 06146-024 CNV IN– Figure 27. ADC Simplified Schematic CIRCUIT INFORMATION The AD7691 is a fast, low power, single-supply, precise, 18-bit ADC using a successive approximation architecture. The part is capable of converting 250,000 samples per second (250 kSPS) and powers down between conversions.
PAGE 15
Data Sheet AD7691 TYPICAL CONNECTION DIAGRAM Figure 29 shows an example of the recommended connection diagram for the AD7691 when multiple supplies are available. V+ REF1 5V 10µF2 100nF V+ 1.8V TO VDD 100nF 15Ω REF 0 TO VREF ADA4841-2 3 V– VDD IN+ 2.7nF AD7691 V+ 4 IN– GND 15Ω VIO SDI SCK 3- OR 4-WIRE INTERFACE5 SDO CNV VREF TO 0 ADA4841-2 3 2.7nF V– 1 SEE VOLTAGE REFERENCE INPUT SECTION FOR REFERENCE SELECTION. 2C REF IS USUALLY A 10µF CERAMIC CAPACITOR (X5R).
PAGE 16
AD7691 Data Sheet DRIVER AMPLIFIER CHOICE SINGLE-TO-DIFFERENTIAL DRIVER Although the AD7691 is easy to drive, the driver amplifier must meet the following requirements: For applications using a single-ended analog signal, either bipolar or unipolar, the ADA4941-1 single-ended-to-differential driver allows for a differential input into the part. The schematic is shown in Figure 32. R5 R6 R3 R4 +5V REF 10µF 15Ω SNRLOSS = 2.
PAGE 17
Data Sheet AD7691 POWER SUPPLY 5V The AD7691 uses two power supply pins: a core supply (VDD) and a digital input/output interface supply (VIO). VIO allows direct interface with any logic between 1.8 V and VDD. To reduce the supplies needed, the VIO and VDD pins can be tied together. The AD7691 is independent of power supply sequencing between VIO and VDD. Additionally, it is very insensitive to power supply variations over a wide frequency range, as shown in Figure 25. VDD = 5V 10 VIO 0.
PAGE 18
AD7691 Data Sheet edges. The data is valid on both SCK edges. Although the rising edge can be used to capture the data, a digital host using the SCK falling edge can allow a faster reading rate, provided it has an acceptable hold time. After the 18th SCK falling edge, or when CNV goes high, whichever occurs first, SDO returns to high impedance. CS MODE, 3-WIRE WITHOUT BUSY INDICATOR This mode is usually used when a single AD7691 is connected to an SPI-compatible digital host.
PAGE 19
Data Sheet AD7691 The data is valid on both SCK edges. Although the rising edge can be used to capture the data, a digital host using the SCK falling edge can allow a faster reading rate, provided it has an acceptable hold time. After the optional 19th SCK falling edge, or when CNV goes high, whichever occurs first, SDO returns to high impedance. CS MODE, 3-WIRE WITH BUSY INDICATOR This mode is usually used when a single AD7691 is connected to an SPI-compatible digital host having an interrupt input.
PAGE 20
AD7691 Data Sheet time elapses and then held high for the maximum possible conversion time to avoid the generation of the busy signal indicator. When the conversion is complete, the AD7691 enters the acquisition phase and powers down. Each ADC result can be read by bringing its SDI input low, which consequently outputs the MSB onto SDO. The remaining data bits are clocked by subsequent SCK falling edges. The data is valid on both SCK edges.
PAGE 21
Data Sheet AD7691 line, this transition can be used as an interrupt signal to initiate the data readback controlled by the digital host. The AD7691 then enters the acquisition phase and powers down. The data bits are clocked out, MSB first, by subsequent SCK falling edges. The data is valid on both SCK edges. Although the rising edge can be used to capture the data, a digital host using the SCK falling edge can allow a faster reading rate, provided it has an acceptable hold time.
PAGE 22
AD7691 Data Sheet readback. When the conversion is complete, the MSB is output onto SDO and the AD7691 enters the acquisition phase and powers down. The remaining data bits stored in the internal shift register are clocked by subsequent SCK falling edges. For each ADC, SDI feeds the input of the internal shift register and is clocked by the SCK falling edge. Each ADC in the chain outputs its data MSB first, and 18 × N clocks are required to read back the N ADCs. The data is valid on both SCK edges.
PAGE 23
Data Sheet AD7691 completed their conversions, the SDO pin of the ADC closest to the digital host (see the AD7691 ADC labeled C in Figure 45) is driven high. This transition on SDO can be used as a busy indicator to trigger the data readback controlled by the digital host. The AD7691 then enters the acquisition phase and powers down. The data bits stored in the internal shift register are clocked out, MSB first, by subsequent SCK falling edges.
PAGE 24
AD7691 Data Sheet APPLICATION HINTS LAYOUT The printed circuit board that houses the AD7691 should be designed so that the analog and digital sections are separated and confined to certain areas of the board. The pin configuration of the AD7691, with its analog signals on the left side and its digital signals on the right side, eases this task. At least one ground plane should be used. It can be common or split between the digital and analog sections.
PAGE 25
Data Sheet AD7691 OUTLINE DIMENSIONS 3.10 3.00 2.90 3.10 3.00 2.90 10 1 5.15 4.90 4.65 6 5 PIN 1 IDENTIFIER 0.50 BSC 0.95 0.85 0.75 15° MAX 1.10 MAX 0.30 0.15 0.70 0.55 0.40 0.23 0.13 6° 0° 091709-A 0.15 0.05 COPLANARITY 0.10 COMPLIANT TO JEDEC STANDARDS MO-187-BA Figure 49.10-Lead Mini Small Outline Package [MSOP] (RM-10) Dimensions shown in millimeters 2.48 2.38 2.23 3.10 3.00 SQ 2.90 0.50 BSC 6 PIN 1 INDEX AREA 10 1.74 1.64 1.49 EXPOSED PAD 0.50 0.40 0.30 5 TOP VIEW 0.
PAGE 26
AD7691 Data Sheet NOTES Rev.
PAGE 27
Data Sheet AD7691 NOTES Rev.