Datasheet

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Channel, ±10 V Input Range, High

Throughput, 24-Bit ∑-∆ ADC

Data Sheet

AD7734

FEATURES

High resolution ADC

24 bits no missing codes

±0.0025% nonlinearity

Optimized for fast channel switching

18-bit p-p resolution (21 bits effective) at 500 Hz

16-bit p-p resolution (19 bits effective) at 2 kHz

14-bit p-p resolution (18 bits effective) at 15 kHz

On-chip per channel system calibration

4 single-ended analog inputs

Input ranges +5 V, ±5 V, +10 V, ±10 V

Overvoltage tolerant

Up to ±16.5 V not affecting adjacent channel

Up to ±50 V absolute maximum

3-wire serial interface

SPI™, QSPI™, MICROWIRE™, and DSP compatible

Schmitt trigger on logic inputs

Single-supply operation

5 V analog supply

3 V or 5 V digital supply

Package: 28-lead TSSOP

APPLICATIONS

PLCs/DCS

Multiplexing applications

Process control

Industrial instrumentation

FUNCTIONAL BLOCK DIAGRAM

SYNC/P1

AIN0

AIN2

AIN1

AIN3

BIASHI

BIASLO

SCLK

DIN

DOUT

RESET

RDY

DGNDMCLKINMCLKOUTAGND AV

BUFFER

REFERENCE

DETECT

REFIN(–) REFIN(+)

AD7734

24-BIT

Σ−∆ ADC

SERIAL

INTERFACE

CONTROL

LOGIC

CLOCK

GENERATOR

CALIBRATION

CIRCUITRY

I/O PORT

MUX

Figure 1.

GENERAL DESCRIPTION

The AD7734 is a high precision, high throughput analog front

end. True 16-bit p-p resolution is achievable with a total

conversion time of 500 µs (2 kHz channel switching), making it

ideally suitable for high resolution multiplexing applications.

The part can be configured via a simple digital interface, which

allows users to balance the noise performance against data

throughput up to a 15.4 kHz.

The analog front end features four single-ended input channels

with unipolar or true bipolar input ranges to ±10 V while

operating from a single +5 V analog supply. The part has an

overrange and underrange detection capability and accepts an

analog input overvoltage to ±16.5 V without degrading the

performance of the adjacent channels.

The differential reference input features “No-Reference” detect

capability. The ADC also supports per channel system calibra-

tion options. The digital serial interface can be configured for

3-wire operation and is compatible with microcontrollers and

digital signal processors. All interface inputs are Schmitt

triggered.

The part is specified for operation over the extended industrial

temperature range of –40°C to +105°C.

Other parts in the AD7734 family are the AD7732 and

the AD7738.

The AD7732 is similar to AD7734, but its analog front end

features two fully differential input channels.

The AD7738 analog front end is configurable for four fully

differential or eight single-ended input channels, features

0.625 V to 2.5 V bipolar/unipolar input ranges, and accepts a

common-mode input voltage from 200 mV to AVDD–300 mV.

The AD7738 multiplexer output is pinned out externally,

allowing the user to implement programmable gain or signal

conditioning before being applied to the ADC.

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

www.analog.com

Summary of content (32 pages)

PAGE 1
Data Sheet 4-Channel, ±10 V Input Range, High Throughput, 24-Bit ∑-∆ ADC AD7734 FEATURES FUNCTIONAL BLOCK DIAGRAM High resolution ADC 24 bits no missing codes ±0.
PAGE 2
AD7734 Data Sheet Table of Contents Features .............................................................................................. 1 Channel Status Registers ........................................................... 18 Applications ....................................................................................... 1 Channel Setup Registers ............................................................ 19 Functional Block Diagram ............................................................
PAGE 3
Data Sheet AD7734 AD7734—SPECIFICATIONS Table 1. (–40°C to +105°C; AVDD = 5 V ± 5%; DVDD = 2.7 V to 3.6 V, or 5 V ± 5%; BIAS0 to BIAS3, BIASHI, REFIN(+) = 2.5 V; BIASLO, REFIN(–) = AGND; AIN Range = ±10 V; fMCLKIN = 6.144 MHz; unless otherwise noted.) Parameter ADC PERFORMANCE CHOPPING ENABLED Conversion Time Rate No Missing Codes 1, 2 Output Noise Resolution Integral Nonlinearity (INL) 1, 2 Integral Nonlinearity (INL)2 Offset Error (Unipolar, Bipolar) 3 Offset Drift vs.
PAGE 4
AD7734 Parameter BIAS0 to 3, BIASHI Pin Impedance1, 8 Input Resistor Matching Input Resistor Temp. Coefficient REFERENCE INPUTS REFIN(+) to REFIN(–) Voltage1, 9 NOREF Trigger Voltage REFIN(+), REFIN(–) Common-Mode Voltage1 Reference Input DC Current 10 SYSTEM CALIBRATION1, 11 Full-Scale Calibration Limit Zero-Scale Calibration Limit Input Span Data Sheet Min 12.5 Typ 15.5 0.2 –30 Max 2.475 2.5 0.5 2.525 0 –1.05 × FS 0.
PAGE 5
Data Sheet Parameter Power Dissipation (Normal Mode) 13 AVDD+DVDD Current (Standby Mode) 14 Power Dissipation (Standby Mode) 14 AD7734 Min Typ 85 100 525 Max 100 1 Unit mW µA µW Test Conditions/Comments Specifications are not production tested but guaranteed by design and/or characterization data at initial product release. See Typical Performance Characteristics. Specifications before calibration. Channel system calibration reduces these errors to the order of the noise.
PAGE 6
AD7734 Data Sheet TIMING SPECIFICATIONS Table 2. (AVDD = 5 V ± 5%; DVDD = 2.7 V to 3.6 V, or 5 V ± 5%; Input Logic 0 = 0 V; Logic 1 = DVDD; unless otherwise noted.) 1 Parameter Master Clock Range t1 t2 Min 1 50 500 Read Operation t4 t5 2 0 Typ Max 6.144 Unit MHz ns ns Test Conditions/Comments ns 0 0 60 80 ns ns 0 0 50 50 0 10 60 80 ns ns ns ns ns ns CS Falling Edge to SCLK Falling Edge Setup Time SCLK Falling Edge to Data Valid Delay DVDD of 4.75 V to 5.25 V DVDD of 2.7 V to 3.
PAGE 7
Data Sheet AD7734 CS t4 t8 t6 SCLK t7 t5 t9 t5A DOUT MSB LSB Figure 2. Read Cycle Timing Diagram CS t11 t16 t14 SCLK t12 DIN t15 t13 MSB LSB Figure 3. Write Cycle Timing Diagram ISINK (800µA AT DVDD = 5V 100µA AT DVDD = 3V) TO OUTPUT PIN 1.6V 50pF ISOURCE (200µA AT DVDD = 5V 100µA AT DVDD = 3V) Figure 4. Load Circuit for Access Time and Bus Relinquish Time Rev.
PAGE 8
AD7734 Data Sheet ABSOLUTE MAXIMUM RATINGS Table 3. TA = 25°C, unless otherwise noted.
PAGE 9
Data Sheet AD7734 TYPICAL PERFORMANCE CHARACTERISTICS 300 25 24 MCLK = 6.144MHz CHOP = 1 250 200 INL – ppm 22 21 20 150 100 19 18 50 17 0 –20 16 1 2 3 4 5 6 7 8 9 10 –15 –10 –5 0 5 10 15 20 AIN DIFFERENTIAL VOLTAGE – V FILTER WORD Figure 8. Typical INL vs. AIN Voltage, AIN Range =±10 V, BIAS0 to BIAS3, BIASHI = 2.5 V, BIASLO = O V Figure 5. No Missing Codes Performance, Chopping Enabled 300 25 24 MCLK = 6.
PAGE 10
AD7734 Data Sheet OUTPUT NOISE AND RESOLUTION SPECIFICATION The AD7734 can be operated with chopping enabled or disabled, allowing the ADC to be programmed to either optimize the throughput rate and channel switching time or to optimize the offset drift performance. Noise tables for these two primary modes of operation are outlined below for a selection of output rates and settling times.
PAGE 11
Data Sheet AD7734 CHOPPING DISABLED The second mode, in which the AD7734 is configured with chopping disabled (CHOP = 0), provides faster conversion time while still maintaining high resolution. Table 7 to Table 9 show the –3 dB frequencies and typical performance versus the channel conversion time and equivalent output data rate, respectively. Table 7 shows the typical output rms noise. Table 8 shows the typical effective resolution based on the rms noise.
PAGE 12
AD7734 Data Sheet PIN CONFIGURATIONS AND FUNCTIONAL DESCRIPTIONS REFIN(–) SCLK 1 MCLKIN 2 25 DOUT RESET 5 AIN1 24 RDY AD7734 BIAS1 23 AGND AIN2 TOP VIEW 22 REFIN(–) SYNC/P1 8 (Not to Scale) 21 REFIN(+) INTBIAS 9 BIAS2 20 BIASHI MUX0 10 19 BIASLO BIAS0 11 18 BIAS3 AIN3 BIAS3 BUFFER 7R R 24-BIT Σ-∆ ADC 7R MUX R AD7734 7R DVDD R CS AIN0 12 17 AIN3 AIN1 13 16 AIN2 BIASLO 15 BIAS2 INTBIAS BIAS1 14 REFERENCE DETECT R=15.
PAGE 13
Data Sheet AD7734 Pin No. 9 Mnemonic INTBIAS 10 MUX0 11, 14, 15, 18 BIAS0–BIAS3 12, 13, 16, 17 19 AIN0–AIN3 BIASLO 20 BIASHI 21 REFIN(+) 22 REFIN(–) 23 24 AGND RDY 25 DOUT 26 DIN 27 28 DVDD DGND Description This pin provides direct access to the analog input’s common node, bypassing the input resistor divider. In normal circuit configuration, this pin is left open circuit. This pin provides direct access to the multiplexer input of Channel 0, bypassing the input resistor divider.
PAGE 14
AD7734 Data Sheet REGISTER DESCRIPTION Table 11. Register Summary Register Addr (hex) 00 Dir Bit 7 Bit 6 W 0 R/W I/O Port 01 R/W P0 P0 Pin Revision 02 R Test 03 R/W ADC Status 04 R Checksum 05 R/W ADC Zero-Scale Calibration 06 R/W ADC Full-Scale 07 R/W Channel Data 1 08–0B R Channel Zero-Scale Cal.1 10–13 R/W Channel Full-Scale Cal.
PAGE 15
Data Sheet AD7734 REGISTER ACCESS The AD7734 is configurable through a series of registers. Some of them configure and control general AD7734 features, while others are specific to each channel. The register data widths vary from 8 bits to 24 bits. All registers are accessed through the communications register, i.e., any communication to the AD7734 must start with a write to the communications register specifying which register will be subsequently read or written.
PAGE 16
AD7734 Data Sheet I/O PORT REGISTER 8 Bits, Read/Write Register, Address 01h, Default Value 30h + Digital Input Value × 40h The bits in this register are used to configure and access the digital I/O port on the AD7734.
PAGE 17
Data Sheet AD7734 ADC STATUS REGISTER 8 Bits, Read-Only Register, Address 04h, Default Value 00h In conversion modes, the register bits reflect the individual channel status. When a conversion is complete, the corresponding channel data register is updated and the corresponding RDY bit is set to 1. When the channel data register is read, the corresponding bit is reset to 0.
PAGE 18
AD7734 Data Sheet CHANNEL ZERO-SCALE CALIBRATION REGISTERS CHANNEL FULL-SCALE CALIBRATION REGISTERS 24 Bits, Read/Write Registers, Address 10h–13h, Default Value 800000h 24 Bits, Read/Write Registers, Address 18h–1Bh, Default Value 200000h These registers hold the particular channel zero-scale calibration coefficients.
PAGE 19
Data Sheet AD7734 CHANNEL SETUP REGISTERS 8 Bits, Read/Write Register, Address 28h–2Bh, Default Value 00h These registers are used to configure the selected channel, to configure its input voltage range, and to set up the corresponding channel status register. Bit Mnemonic Default Bit 7 0 0 Bit 6 0 0 Bit 5 0 0 Bit 4 Stat OPT 0 Bit 3 ENABLE 0 Bit 2 0 0 Bit 1 RNG1 0 Bit 0 RNG0 0 Bit 7–5 4 Mnemonic 0 Stat OPT 3 ENABLE 2 1–0 0 RNG1–RNG0 Description These bits must be 0 for proper operation.
PAGE 20
AD7734 Data Sheet MODE REGISTER 8 Bits, Read/Write Register, Address 38h–3Bh, Default Value 00h The mode register configures the part and determines its operating mode. Writing to the mode register clears the ADC status register, sets the RDY pin to a logic high level, exits all current operations, and starts the mode specified by the mode bits. The AD7734 contains only one mode register.
PAGE 21
Data Sheet AD7734 MD2 MD1 MD0 Operating Mode 0 0 0 Idle Mode The default mode after power-on or reset. The AD7734 automatically returns to this mode after any calibration or after a single conversion. 0 0 1 Continuous Conversion Mode The AD7734 performs a conversion on the specified channel.
PAGE 22
AD7734 Data Sheet DIGITAL INTERFACE DESCRIPTION The RESET pin can be used to reset the AD7734. When not used, connect this pin to DVDD. HARDWARE The AD7734 serial interface can be connected to the host device via the serial interface in several different ways. The CS pin can be used to select the AD7734 as one of several circuits connected to the host serial interface. When CS is high, the AD7734 ignores the SCLK and DIN signals and the DOUT pin goes to the high impedance state.
PAGE 23
Data Sheet AD7734 RESET The AD7734 can be reset by the RESET pin or by writing a reset sequence to the AD7734 serial interface. CS SCLK The reset sequence is N × 0 + 32 × 1, which could be the data sequence 00h + FFh + FFh + FFh + FFh in a byte-oriented interface. The AD7734 also features a power-on reset with a trip point of 2 V and goes to the defined default state after power-on. It is the system designer’s responsibility to prevent an unwanted write operation to the AD7734.
PAGE 24
AD7734 Data Sheet DUMP MODE When the DUMP bit in the mode register is set to 1, the channel status register will be read immediately by a read of the channel data register, regardless of whether the status or the data register has been addressed through the communications register. The DIN pin should not be high while reading 24-bit data in dump mode; otherwise, the AD7734 will be reset.
PAGE 25
Data Sheet AD7734 START CONTINUOUS CONVERSION READ READ DATA DATA CH0 CH1 READ READ DATA DATA CH0 CH1 SERIAL INTERFACE RDY CH1 CONVERSION CH0 CONVERSION CH0 CONVERSION CH1 CONVERSION CH0 CONVERSION Figure 20. Continuous Conversion, CH0 and CH1, RDYFN = 1 START CONTINUOUS CONVERSION SERIAL INTERFACE RDY CH0 CONVERSION CH1 CONVERSION CH0 CONVERSION CH1 CONVERSION CH0 CONVERSION Figure 21.
PAGE 26
AD7734 Data Sheet CIRCUIT DESCRIPTION The AD7734 is a sigma-delta ADC that is intended for the measurement of wide dynamic range, low frequency signals in industrial process control, instrumentation, and PLC systems. It contains thin film resistor dividers, a multiplexer, an input buffer, a sigma-delta (or charge balancing) ADC, a digital filter, a clock oscillator, a digital I/O port, and a serial communications interface. ANALOG FRONT END The AD7734 features four single-ended analog inputs.
PAGE 27
Data Sheet AD7734 ANALOG INPUT’S EXTENDED VOLTAGE RANGE The AD7734 output data code span corresponds to the nominal input voltage range. The ADC is functional outside the nominal input voltage range, but the performance might degrade. The sigma-delta modulator was designed to fully cover a ±11.6 V analog input voltage; outside this range, the performance might degrade more rapidly. The adjacent channels are not affected by up to ±16.5 V analog input voltage (Figure 8).
PAGE 28
AD7734 Data Sheet MULTIPLEXER, CONVERSION, AND DATA OUTPUT TIMING The RDY pin goes high during the scaling time, regardless of its previous state. The relevant RDY bit is set in the ADC status register and in the channel status register, and the RDY pin goes low when the channel data register is updated and the channel conversion cycle is finished. If in continuous conversion mode, the part will automatically continue with a conversion cycle on the next enabled channel.
PAGE 29
Data Sheet AD7734 FREQUENCY RESPONSE VOLTAGE REFERENCE INPUTS The sigma-delta modulator runs at ½ the MCLK frequency, which is effectively the sampling frequency. Therefore, the Nyquist frequency is ¼ the MCLK frequency. The digital filter, in association with the modulator, features the frequency response of a first order low-pass filter. The –3 dB point is close to the frequency of 1/channel conversion time. The roll-off is –20 dB/dec up to the Nyquist frequency.
PAGE 30
AD7734 Data Sheet I/O PORT The AD7734 P0 pin can be used as a general-purpose digital I/O pin. The P1 pin (SYNC/P1) can be used as a generalpurpose digital I/O pin or to synchronize the AD7734 with other devices in the system. When the SYNC bit in the I/O port register is set and the SYNC pin is low, the AD7734 does not process any conversion.
PAGE 31
Data Sheet AD7734 DVDD AVDD + 10µF + 0.1µF ANALOG INPUTS 0.1µF AIN0(+) 4 TO 20mA 7R MCLKIN BIAS0(+) R=15.5kΩ 500R 0V TO 10V –10V TO +10V 0V TO 5V AIN1 7R BIAS1 R AIN2 7R BIAS2 R AIN3 7R BIAS3 R CLOCK GENERATOR +VIN + 10µF VOUT +2.5V AD780 0.01µF 10µF MCLKOUT 33pF 24-BIT Σ-∆ ADC MUX DVDD BUFFER RESET BIASHI R BIASLO 7R AD7734 REFIN(+) SERIAL INTERFACE AND CONTROL LOGIC REFIN(–) + 6.
PAGE 32
AD7734 Data Sheet OUTLINE DIMENSIONS 9.80 9.70 9.60 28 15 4.50 4.40 4.30 6.40 BSC 1 14 PIN 1 0.65 BSC 0.15 0.05 COPLANARITY 0.10 0.30 0.19 1.20 MAX SEATING PLANE 0.20 0.09 8° 0° 0.75 0.60 0.45 COMPLIANT TO JEDEC STANDARDS MO-153-AE Figure 30. 28-Lead Thin Shrink Small Outline Package [TSSOP] (RU-28) Dimensions shown in millimeters Table 18.