Datasheet

ManualsBrandsANALOG DEVICES ManualsData collecting ICsData acquisition IC - AD converter (ADC) External , Internal SOIC 28 W

Summary of content (12 pages)

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(V = +5 V ⴞ 5%; AGND = DGND = O V; AD7776/AD7777/AD7778–SPECIFICATIONS CLKIN = 8 MHz; RTN = O V; C = 10 nF; all specifications T to T unless otherwise noted.
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AD7776/AD7777/AD7778 TIMING SPECIFICATIONS1, 2 (V CC = +5 V ⴞ 5%; AGND = DGND = 0 V; all specifications TMIN to TMAX, unless otherwise noted.) Parameter Label Limit at TMIN to TMAX Unit INTERFACE TIMING CS Falling Edge to WR or RD Falling Edge WR or RD Rising Edge to CS Rising Edge WR Pulsewidth CS or RD Active to Valid Data 3, 4 Bus Relinquish Time after RD3, 5 t1 t2 t3 t4 t5 0 0 53 60 10 45 55 10 1.5 tCLKIN 2.5 tCLKIN + 70 ns min ns min ns min ns max ns min ns max ns min ns min ns min ns max 19.
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AD7776/AD7777/AD7778 ABSOLUTE MAXIMUM RATINGS* PQFP Package, Power Dissipation . . . . . . . . . . . . . . 500 mW θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 95°C/W Lead Temperature, Soldering Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . 215°C Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C (TA = +25°C unless otherwise noted) VCC to AGND or DGND . . . . . . . . . . . . . . . . . . –0.3 V, +7 V AGND, RTN to DGND . . . . . . . . . .
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AD7776/AD7777/AD7778 PIN FUNCTION DESCRIPTION Mnemonic Description VCC +5 V Power Supply. AGND Analog Ground. DGND Digital Ground. Ground reference for digital circuitry. DB0–DB9 Input/Output Data Bus. This is a bidirectional data port from which ADC output data may be read and to which control register data may be written. BUSY/INT Busy/Interrupt Output. Active low logic output indicating A/D converter status.
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AD7776/AD7777/AD7778 CONTROL REGISTER AD7778 The control register is 10-bit wide and can only be written to. On power-on, all locations in the control register are automatically loaded with 0s. For the single channel AD7776, locations CR0 to CR6 of the control register are “don’t cares.” For the quad channel AD7777, locations CR2 and CR5 are “don’t cares.” Individual bit functions are described below. CR5 0 0 0 0 1 1 1 1 CR0–CR2: Channel Address Locations.
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AD7776/AD7777/AD7778 ADC Conversion Start Timing Power-Down Figure 6 shows the operating waveforms for the start of a conversion cycle. On the rising edge of WR, the conversion cycle starts with the acquisition and tracking of the selected ADC channel, AIN1–8. The analog input voltage is held 40 ns (typically) after the first rising edge of CLKIN following four complete CLKIN cycles. If tD in Figure 6 is greater than 12 ns, the falling edge of CLKIN as shown is seen as the first falling clock edge.
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AD7776/AD7777/AD7778 Figure 10 shows the interface with the 80C196KB at 12 MHz and the 80C196KC at 16 MHz. One wait state is required with the 16 MHz machine. The 80C196 is configured to operate with a 16-bit multiplexed address/data bus. Microprocessor Interfacing Circuits The AD7776/AD7777/AD7778 family of ADCs is intended to interface to DSP machines such as the ADSP-2101, ADSP-2105, the TMS320 family and microcontrollers such as the 80C196 family.
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AD7776/AD7777/AD7778 Table I. AD7776/AD7777/AD7778 Truth Table for Microprocessor Interfacing CS RD WR DB0–DB9 Function/Comments 1 X* X* High Z Data Port High Impedance 0 1 j CR Data Load control register (CR) data to control register and start a conversion. 0 k 1 ADC Data ADC data placed on data bus. Depending upon location CR6 of the control register, one or two Read instructions are required. If CR6 is low, i.e.
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AD7776/AD7777/AD7778 Short Circuit Current Figure 11 shows a 2048-point FFT plot for a single channel of the AD7778 with an input signal of 99.88 kHz. The SNR is 58.71 dB. It can be seen that most of the harmonics are buried in the noise floor. It should be noted that the harmonics are taken into account when calculating the S/(N+D). This is defined as the maximum current which flows either into or out of the REFOUT pin if this pin is shorted to any potential between 0 V and VCC.
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AD7776/AD7777/AD7778 Changing the Analog Input Voltage Range By biasing the RTN pin above AGND, it is possible to change the analog input voltage range from its VBIAS ± VSWING format to a more traditional 0 V to VREF range. The new input range can be described as VOFFSET to (VOFFSET + REFIN ) where 0 V ≤ VOFFSET ≤ 1 V. To produce this range, the RTN pin must be biased to (REFIN – 2 VOFFSET). For instance, if RTN is tied to REFOUT, then the analog input range becomes 0 V to 2 V.
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AD7776/AD7777/AD7778 OUTLINE DIMENSIONS 28-Lead Plastic Dual-in-Line Package [PDIP] (N-28) C01196–0–10/02(A) Dimensions shown in millimeters and (inches) 39.70 (1.5630) 35.10 (1.3819) 28 15 14.73 (0.5799) 12.32 (0.4850) 1 14 1.52 (0.0598) 0.38 (0.0150) 6.35 (0.2500) MAX 15.87 (0.6248) 15.24 (0.6000) 3.81 (0.1500) MIN 5.05 (0.1988) 1.77 0.56 (0.0220) 2.54 3.18 (0.1252) 0.36 (0.0142) (0.1000) (0.0697) MAX BSC 4.95 (0.1949) 3.18 (0.1252 ) 0.38 (0.0150) 0.20 (0.