Datasheet

AD7776/AD7777/AD7778
–3–
REV. A
TIMING SPECIFICATIONS
1, 2
(V
CC
= +5 V ⴞ 5%; AGND = DGND = 0 V; all specifications T
MIN
to T
MAX
, unless otherwise noted.)
t
3
t
11
t
10
t
9
t
8
FIRST
CONVERSION
FINISHED
(CR6 = 0)
SECOND
CONVERSION
FINISHED (CR6 = 1)
AD7777/AD7778 ONLY
t
9
BUSY
(CR8 = 0)
INT
(CR8 = 1)
t
10
WR, RD
Figure 3. BUSY / INT Timing
I
OL
1.6mA
+2.1V
I
OH
200µA
C
OUT
100pF
DB n
Figure 4. Load Circuit for Bus Timing Characteristics
t
1
CS
t
2
t
4
t
5
RD
DB0–DB9
Figure 1. Read Cycle Timing
t
1
CS
t
2
t
6
WR
DB0–DB9
t
3
t
7
Figure 2. Write Cycle Timing
Parameter Label Limit at T
MIN
to T
MAX
Unit Test Conditions/Comments
INTERFACE TIMING
CS Falling Edge to WR or RD Falling Edge t
1
0 ns min
WR or RD Rising Edge to CS Rising Edge t
2
0 ns min
WR Pulsewidth t
3
53 ns min
CS or RD Active to Valid Data
3, 4
t
4
60 ns max Timed from Whichever Occurs Last
Bus Relinquish Time after RD
3, 5
t
5
10 ns min
45 ns max
Data Valid to WR Rising Edge t
6
55 ns min
Data Valid after WR Rising Edge t
7
10 ns min
WR Rising Edge to BUSY Falling Edge t
8
1.5 t
CLKIN
ns min CR9 = 0
2.5 t
CLKIN
+ 70 ns max
WR Rising Edge to BUSY Rising Edge or
INT Falling Edge t
9
19.5 t
CLKIN
+ 70 ns max Single Conversion, CR6 = 0
t
10
33.5 t
CLKIN
+ 70 ns max Double Conversion, CR6 = 1
WR or RD Falling Edge to INT Rising Edge t
11
60 ns max CR9 = 1
NOTES
1
See Figures 1 to 3.
2
All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.
3
100% production tested. All other times are guaranteed by design, not production tested.
4
t
4
is measured with the load circuit of Figure 4 and defined as the time required for an output to cross 0.8 V or 2.4 V.
5
t
5
is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 4. The measured time is then extrapolated back
to remove the effects of charging or discharging the 100 pF capacitor. This means that the time t
5
quoted above is the true bus relinquish time of the device and, as
such, is independent of the external bus loading capacitance.
Specifications subject to change without notice.