Datasheet

AD7813
–3–
REV. C
ORDERING GUIDE
Linearity Package Package
Model Error Description Option
AD7813YN ± 1 LSB Plastic DIP N-16
AD7813YR ± 1 LSB Small Outline IC R-16A
AD7813YRU ± 1 LSB Thin Shrink Small Outline RU-16
(TSSOP)
TIMING CHARACTERISTICS
1, 2
Parameter V
DD
= 3 V  10% V
DD
= 5 V  10% Unit Conditions/Comments
t
POWER-UP
1.5 1.5 µs (max) Power-Up Time of AD7813 after Rising Edge of CONVST.
t
1
2.3 2.3 µs (max) Conversion Time.
t
2
20 20 ns (min) CONVST Pulsewidth.
t
3
30 30 ns (max) CONVST Falling Edge to BUSY Rising Edge Delay.
t
4
0 0 ns (min) CS to RD Setup Time.
t
5
0 0 ns (min) CS Hold Time after RD High.
t
6
3
10 10 ns (max) Data Access Time after RD Low.
t
7
3, 4
10 10 ns (max) Bus Relinquish Time after RD High.
5 5 ns (min)
t
8
10 10 ns (min) Minimum Time Between MSB and LSB Reads.
t
9
3
50 50 ns (min) Rising Edge of CS or RD to Falling Edge of CONVST Delay.
NOTES
1
Sample tested to ensure compliance.
2
See Figures 12, 13 and 14.
3
These numbers are measured with the load circuit of Figure 1. They are defined as the time required for the o/p to cross 0.8 V or 2.4 V for V
DD
= 5 V ± 10% and
0.4 V or 2 V for V
DD
= 3 V ± 10%.
4
Derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated back
to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t
7
, quoted in the Timing Characteristics is the true bus relinquish time
of the part and as such is independent of external bus loading capacitances.
(–40C to +105C, unless otherwise noted)
ABSOLUTE MAXIMUM RATINGS*
V
DD
to DGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
Digital Input Voltage to DGND
(CONVST, RD, CS) . . . . . . . . . . . . . . –0.3 V, V
DD
+ 0.3 V
Digital Output Voltage to DGND
(BUSY, DB0–DB7) . . . . . . . . . . . . . . . –0.3 V, V
DD
+ 0.3 V
REF
IN
to AGND . . . . . . . . . . . . . . . . . . . –0.3 V, V
DD
+ 0.3 V
Analog Input . . . . . . . . . . . . . . . . . . . . . . –0.3 V, V
DD
+ 0.3 V
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C
Plastic DIP Package, Power Dissipation . . . . . . . . . . 450 mW
θ
JA
Thermal Impedance . . . . . . . . . . . . . . . . . . . . 105°C/W
Lead Temperature, (Soldering 10 sec) . . . . . . . . . . . . 260°C
SOIC Package, Power Dissipation . . . . . . . . . . . . . . . 450 mW
θ
JA
Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 75°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . 215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C
SSOP Package, Power Dissipation . . . . . . . . . . . . . . . 450 mW
θ
JA
Thermal Impedance . . . . . . . . . . . . . . . . . . . . 115°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . 215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute maximum rating condi-
tions for extended periods may affect device reliability.
1.6V
200AI
OL
200A
I
OH
C
L
50pF
TO
OUTPUT
PIN
Figure 1. Load Circuit for Digital Output Timing
Specifications
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD7813 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE