Datasheet

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MOS

Quad 14-Bit DACs

AD7834/AD7835

Rev. D

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FEATURES

Four 14-bit DACs in one package

AD7834—serial loading

AD7835—parallel 8-bit/14-bit loading

Voltage outputs

Power-on reset function

Maximum/minimum output voltage range of ±8.192 V

Maximum output voltage span of 14 V

Common voltage reference inputs

User-assigned device addressing

Clear function to user-defined voltage

Surface-mount packages

AD7834—28-lead SOIC and PDIP

AD7835—44-lead MQFP and PLCC

APPLICATIONS

Process control

Automatic test equipment

General-purpose instrumentation

GENERAL DESCRIPTION

The AD7834 and AD7835 contain four 14-bit DACs on one

monolithic chip. The AD7834 and AD7835 have output

voltages in the range ±8.192 V with a maximum span of 14 V.

The AD7834 is a serial input device. Data is loaded in 16-bit

format from the external serial bus, MSB first after two leading 0s,

into one via DIN, SCLK, and

FSYNC

. The AD7834 has five

dedicated package address pins, PA0 to PA4, that can be wired

to AGND or V

to permit up to 32 AD7834s to be individually

addressed in a multipackage application.

The AD7835 can accept either 14-bit parallel loading or double-

byte loading, where right-justified data is loaded in one 8-bit

byte and one 6-bit byte. Data is loaded from the external bus

into one of the input latches under the control of the

BYSHF

, and DAC channel address pins, A0 to A2.

With each device, the

LDAC

signal is used to update all four

DAC outputs simultaneously, or individually, on reception of

new data. In addition, for each device, the asynchronous

CLR

input can be used to set all signal outputs, V

OUT

1 to V

OUT

4, to

the user-defined voltage level on the device sense ground pin,

DSG. On power-on, before the power supplies have stabilized,

internal circuitry holds the DAC output voltage levels to within

±2 V of the DSG potential. As the supplies stabilize, the DAC

output levels move to the exact DSG potential (assuming

CLR

exercised).

The AD7834 is available in a 28-lead 0.3" SOIC package and a

28-lead 0.6" PDIP package, and the AD7835 is available in a

44-lead MQFP package and a 44-lead PLCC package.

FUNCTIONAL BLOCK DIAGRAMS

×1

DAC 1

LATCH

INPUT

REF

(–)

REF

(+)

OUT

PAEN

PA0

PA1

PA2

PA3

PA4

CONTROL

LOGIC

AND

ADDRESS

DECODE

SERIAL-TO-

PARALLEL

CONVERTER

DIN

SCLK

×1

DAC 2

LATCH

INPUT

×1

DAC 3

LATCH

×1

DAC 4

LATCH

INPUT

AD7834

OUT

AGND DGND DSG

FSYNC

LDAC

CLR

INPUT

DAC 1

DAC 2

DAC 3

DAC 4

01006-001

×1

DAC 1

LATCH

INPUT

REF

(–)

REF

(+)

OUT

BYSHF

DB13

DB0

×1

DAC 2

LATCH

DAC 2

INPUT

×1

DAC 3

LATCH

INPUT

×1

DAC 4

LATCH

INPUT

DAC 1

AD7835

OUT

AGND DGND

LDAC

DSGB

CLR

DSGA

DAC 4

DAC 3

REF

(–)B

REF

(+)B

ADDRESS

DECODE

INPUT

BUFFER

01006-002

Figure 1. AD7834 Figure 2. AD7835

Summary of content (28 pages)

PAGE 1
LC2MOS Quad 14-Bit DACs AD7834/AD7835 into one via DIN, SCLK, and FSYNC. The AD7834 has five dedicated package address pins, PA0 to PA4, that can be wired to AGND or VCC to permit up to 32 AD7834s to be individually addressed in a multipackage application. FEATURES Four 14-bit DACs in one package AD7834—serial loading AD7835—parallel 8-bit/14-bit loading Voltage outputs Power-on reset function Maximum/minimum output voltage range of ±8.
PAGE 2
AD7834/AD7835 TABLE OF CONTENTS Features .............................................................................................. 1 Power-On with CLR Low, LDAC High ................................... 17 Applications....................................................................................... 1 Power-On with LDAC Low, CLR High ................................... 17 General Description .........................................................................
PAGE 3
AD7834/AD7835 SPECIFICATIONS VCC = 5 V ± 5%; VDD = 15 V ± 5%; VSS = −15 V ± 5%; AGND = DGND = 0 V; TA 1 = TMIN to TMAX, unless otherwise noted. Table 1. Parameter ACCURACY Resolution Relative Accuracy Differential Nonlinearity Full-Scale Error TMIN to TMAX Zero-Scale Error Gain Error Gain Temperature Coefficient 2 A B S Unit 14 ±2 ±0.9 14 ±1 ±0.9 14 ±2 ±0.9 Bits LSB max LSB max ±5 ±4 ±0.5 4 ±5 ±4 ±0.5 4 ±8 ±5 ±0.
PAGE 4
AD7834/AD7835 VCC = 5 V ± 5%; VDD = 12 V ± 5%; VSS = −12 V ± 5%; AGND = DGND = 0 V; TA 1 = TMIN to TMAX, unless otherwise noted. Table 2. Parameter ACCURACY Resolution Relative Accuracy Differential Nonlinearity Full-Scale Error TMIN to TMAX Zero-Scale Error Gain Error Gain Temperature Coefficient 2 A B S Unit 14 ±2 ±0.9 14 ±1 ±0.9 14 ±2 ±0.9 Bits LSB max LSB max ±5 ±4 ±0.5 4 20 50 ±5 ±4 ±0.5 4 20 50 ±8 ±5 ±0.5 4 20 50 mV max mV max mV typ ppm FSR/°C typ ppm FSR/°C max μV max 30 ±1 0/8.
PAGE 5
AD7834/AD7835 AC PERFORMANCE CHARACTERISTICS These characteristics are included for design guidance and are not subject to production testing. Table 3. Parameter DYNAMIC PERFORMANCE Output Voltage Settling Time A B S Unit (typ) Test Conditions/Comments 10 10 10 μs Digital-to-Analog Glitch Impulse 120 120 120 nV-s DC Output Impedance Channel-to-Channel Isolation DAC-to-DAC Crosstalk Digital Crosstalk 0.5 100 25 3 0.5 100 25 3 0.
PAGE 6
AD7834/AD7835 TIMING SPECIFICATIONS VCC = 5 V ± 5%; VDD = 11.4 V to 15.75 V; VSS = −11.4 V to −15.75 V; AGND = DGND = 0 V 1 . Table 4.
PAGE 7
AD7834/AD7835 ABSOLUTE MAXIMUM RATINGS TA = 25°C unless otherwise noted. Transient currents of up to 100 mA do not cause SCR latch-up. VCC must not exceed VDD by more than 0.3 V. If it is possible for this to happen during power supply sequencing, the diode protection scheme shown in Figure 5 can be used to provide protection. VDD Table 5.
PAGE 8
AD7834/AD7835 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS VSS 1 28 AGND DSG 2 27 NC VREF(–) 3 26 NC VREF(+) 4 25 NC NC 5 24 NC VOUT2 6 23 VDD DGND 8 21 VOUT3 VCC 9 20 CLR SCLK 10 19 LDAC DIN 11 18 FSYNC PA0 12 17 PAEN PA1 13 16 PA4 PA2 14 15 PA3 AD7834 NC = NO CONNECT 01006-006 TOP VIEW VOUT4 7 (Not to Scale) 22 VOUT1 Figure 6. AD7834 PDIP and SOIC Pin Configuration Table 7. AD7834 Pin Function Descriptions Pin No.
PAGE 9
NC VREF(–)B 1 VREF(+)B VSS VDD 2 AGND NC 3 NC VREF(–)A 4 44 43 42 41 40 PIN 1 IDENTIFIER NC 7 33 NC PIN 1 IDENTIFIER 5 39 NC 32 DSGB DSGA 8 38 DSGB VOUT1 3 31 VOUT3 VOUT1 9 37 VOUT3 VOUT2 4 30 VOUT4 VOUT2 10 DSGA 2 NC 5 AD7835 A2 6 TOP VIEW (Not to Scale) A1 7 A0 8 29 DB13 NC 11 28 DB12 A2 12 27 DB11 A1 13 26 DB10 A0 14 36 VOUT4 35 DB13 AD7835 34 DB12 TOP VIEW (Not to Scale) 33 DB11 32 DB10 CLR 9 25 DB9 CLR 15 31 DB9 LDAC 10 24 DB8 LDAC 16 30 DB8 BYSHF
PAGE 10
AD7834/AD7835 Pin No. MQFP 16 to 29 Pin No. PLCC 22 to 35 Pin Mnemonic DB0 to DB13 32 38 DSGB 36, 35 42, 41 VREF(+)B, VREF(−)B Description Parallel Data Inputs. The AD7835 can accept a straight 14-bit parallel word on DB0 to DB13, where DB13 is the MSB and the BYSHF input is hardwired to a logic high. Alternatively for byte loading, the bottom eight data inputs, DB0 to DB7, are used for data loading, and the top six data inputs, DB8 to DB13, should be hardwired to a logic low.
PAGE 11
AD7834/AD7835 TYPICAL PERFORMANCE CHARACTERISTICS 1.0 0.50 0.8 0.45 0.6 0.40 0.4 0.35 0.2 0.30 0.15 0.10 0 2 4 6 8 10 CODE/1000 12 14 DAC 2 0.20 –0.6 –1.0 DAC 4 0.25 –0.4 –0.8 DAC 3 TEMP = 25°C ALL DACs FROM 1 DEVICE 0.05 0 16 01006-012 INL (LSB) 0 –0.2 01006-009 INL (LSB) DAC 1 0 2.5 5.0 8.0 VREF(+) (V) Figure 9. Typical INL Plot Figure 12. Typical INL vs. VREF(+), VREF(+) – VREF(−) = 5 V 0.5 0.8 0.4 ALL DACs FROM ONE DEVICE 0.7 0.3 0.6 DAC 1 DAC 3 0.5 0.
PAGE 12
AD7834/AD7835 0.7 0.6 –2.985 8 VERT = 100mV/DIV HORIZ = 1μs/DIV VERT = 10mV/DIV HORIZ = 1µs/DIV 6 –3.005 4 –3.025 0.3 VOLTS VOLTS 0.4 0.2 2 VREF (+) = +7V VREF (–) = –3V –3.065 0 0.1 –3.045 VOLTS 0.5 0 01006-015 VERT = 2V/DIV HORIZ = 1µs/DIV –0.2 Figure 15. Typical Digital/Analog Glitch Impulse 6 7.225 4 7.200 2 VREF(+) = +7V VREF(–) = –3V 7.175 VOLTS VERT = 2V/DIV HORIZ = 1.2μs/DIV 7.150 0 7.125 –2 VERT = 25mV/DIV HORIZ = 2.5μs/DIV 7.
PAGE 13
AD7834/AD7835 TERMINOLOGY Relative Accuracy Relative accuracy or endpoint linearity is a measure of the maximum deviation from a straight line passing through the endpoints of the DAC transfer function. It is measured after adjusting for zero error and full-scale error. It is normally expressed in LSBs or as a percentage of full-scale reading. Differential Nonlinearity Differential nonlinearity is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes.
PAGE 14
AD7834/AD7835 THEORY OF OPERATION DAC ARCHITECTURE Table 9. D23 Control Each channel consists of a segmented 14-bit R-2R voltage-mode DAC. The full-scale output voltage range is equal to the entire reference span of VREF(+) – VREF(−). The DAC coding is straight binary; all 0s produce an output of VREF(−); all 1s produce an output of VREF(+) − 1 LSB. D23 0 1 Control Function Ignore the following 23 bits of information. Use the following 23 bits of address and data as normal.
PAGE 15
AD7834/AD7835 NOTE: D23 IS THE FIRST BIT TRANSMITTED IN THE SERIAL WORD.
PAGE 16
AD7834/AD7835 BIPOLAR CONFIGURATION +15V +5V VDD VCC In Figure 20, full-scale and bipolar zero adjustments are provided by varying the gain and balance on the AD588. R2 varies the gain on the AD588 while R3 adjusts the offset of both the +5 V and –5 V outputs together with respect to ground.
PAGE 17
AD7834/AD7835 CONTROLLED POWER-ON OF THE OUTPUT STAGE G1 A block diagram of the output stage of the AD7834/AD7835 is shown in Figure 21. It is capable of driving a load of 10 kΩ in parallel with 200 pF. G1 to G6 are transmission gates used to control the power-on voltage present at VOUT. G1 and G2 are also used in conjunction with the CLR input to set VOUT to the userdefined voltage present at the DSG pin. G6 DAC VOUT G3 G4 G2 R 01006-023 G5 G1 G6 DAC DSG VOUT Figure 23.
PAGE 18
AD7834/AD7835 DSG VOLTAGE RANGE During power-on, the VOUT pins of the AD7834/AD7835 are connected to the relevant DSG pins via G6 and the thin-film resistor, R. The DSG potential must obey the maximum ratings at all times. Thus, the voltage at DSG must always be within the range VSS – 0.3 V to VDD + 0.3 V.
PAGE 19
AD7834/AD7835 POWER-ON OF THE AD7834/AD7835 In some systems, it is necessary to introduce one or more Schottky diodes between pins to prevent the above situations arising at power-on. These diodes are shown in Figure 25. However, in most systems, with careful consideration given to power supply sequencing, the above rules are adhered to, and protection diodes are not necessary. Rev. D | Page 19 of 28 VREF(+) AD78341 SD103C 1N5711 1N5712 VREF(–) 1ADDITIONAL PINS OMITTED FOR CLARITY Figure 25.
PAGE 20
AD7834/AD7835 MICROPROCESSOR INTERFACING A serial interface between the AD7834 and the 80C51 microcontroller is shown in Figure 26. TXD of the 80C51 drives SCLK of the AD7834, while RXD drives the serial data line of the part. The 80C51 provides the LSB of its SBUF register as the first bit in the serial data stream. The AD7834 expects the MSB of the 24-bit write first.
PAGE 21
AD7834/AD7835 CLOCK/ TIMER TMS32020/ TMS320C251 DSP56000/ DSP560011 SC0 CLR SC1 LDAC SC2 FSYNC SCK SCLK STD DIN PINS OMITTED FOR CLARITY SCLK CLKX DIN DX PINS OMITTED FOR CLARITY Figure 30. AD7834 to TMS32020/TMS320C25 Interface INTERFACING THE AD7835—16-BIT INTERFACE The AD7835 can be interfaced to a variety of microcontrollers or DSP processors, both 8-bit and 16-bit. Figure 31 shows the AD7835 interfaced to a generic 16-bit microcontroller/DSP processor.
PAGE 22
AD7834/AD7835 INTERFACING THE AD7835—8-BIT INTERFACE Figure 32 shows an 8-bit interface between the AD7835 and a generic 8-bit microcontroller/DSP processor. Pin D13 to Pin D8 of the AD7835 are tied to DGND. Pin D7 to Pin D0 of the processor are connected to Pin D7 to Pin D0 of the AD7835. BYSHF is driven by the A0 line of the processor. This maps the DAC upper bits and lower bits into adjacent bytes in the processor address space. Table 14 shows the truth table for addressing the DACs in the AD7835.
PAGE 23
AD7834/AD7835 APPLICATIONS INFORMATION Figure 33 shows how the package address pins of the AD7834 are used to address multiple AD7834s. This figure shows only 10 devices, but up to 32 AD7834s can each be assigned a unique address by hardwiring each of the package address pins to VCC or DGND. Normal operation of the device occurs when PAEN is low.
PAGE 24
AD7834/AD7835 VOFFSET +15V –15V 2 3 1 +15V VREF(+)A 15 14 AD588 VOUT2 DSG A 0.
PAGE 25
AD7834/AD7835 OUTLINE DIMENSIONS 18.10 (0.7126) 17.70 (0.6969) 15 28 7.60 (0.2992) 7.40 (0.2913) 1 14 10.65 (0.4193) 10.00 (0.3937) 2.65 (0.1043) 2.35 (0.0925) 0.30 (0.0118) 0.10 (0.0039) COPLANARITY 0.10 1.27 (0.0500) BSC 0.51 (0.0201) 0.31 (0.0122) SEATING PLANE 0.75 (0.0295) 0.25 (0.0098) 45° 8° 0° 0.33 (0.0130) 0.20 (0.0079) 1.27 (0.0500) 0.40 (0.
PAGE 26
AD7834/AD7835 0.180 (4.57) 0.165 (4.19) 0.048 (1.22) 0.042 (1.07) 0.056 (1.42) 0.042 (1.07) 6 40 39 7 0.021 (0.53) 0.013 (0.33) PIN 1 IDENTIFIER 17 0.630 (16.00) 0.590 (14.99) 0.050 (1.27) BSC TOP VIEW (PINS DOWN) (PINS UP) 0.032 (0.81) 0.026 (0.66) 29 28 18 BOTTOM VIEW 0.656 (16.66) SQ 0.650 (16.51) 0.045 (1.14) R 0.025 (0.64) 0.120 (3.05) 0.090 (2.29) 0.695 (17.65) SQ 0.685 (17.
PAGE 27
AD7834/AD7835 ORDERING GUIDE Model AD7834AR AD7834AR-REEL AD7834ARZ 1 AD7834ARZ-REEL1 AD7834BR AD7834BR-REEL AD7834BRZ1 AD7834BRZ-REEL1 AD7834AN AD7834ANZ1 AD7834BN AD7834BNZ1 AD7835AP AD7835AP-REEL AD7835APZ1 AD7835APZ-REEL1 AD7835AS AD7835AS-REEL AD7835ASZ1 AD7835ASZ-REEL1 1 Temperature Range −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C