a FEATURES Single 5 V Supply 333 kSPS Throughput Rate/ⴞ2 LSB DNL—A Grade 285 kSPS Throughput Rate/ⴞ1 LSB DNL—K Grade A and K Grades Guaranteed to 125ⴗC/238 kSPS Throughput Rate Pseudo-Differential Input with Two Input Ranges System and Self-Calibration with Autocalibration on Power-Up Read/Write Capability of Calibration Data Low Power: 60 mW Typ Power-Down Mode: 5 W Typ Power Consumption Flexible Serial Interface: 8051/SPI®/QSPI™/P Compatible 24-Lead PDIP, SOIC, and SSOP Packages 14-Bit 333 kSPS Serial
AD7851 TABLE OF CONTENTS FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . 1 PRODUCT HIGHLIGHTS . . . . . . . . . . . . . . . . . . . . . . . . . 1 SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 TIMING SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . 5 TYPICAL TIMING DIAGRAMS . . . . . . . . . . . . . . . . . . . . 6 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . .
AD7851 1, 2 SPECIFICATIONS A Grade: f = 7 MHz (–40ⴗC to +85ⴗC), f CLKIN SAMPLE = 333 kHz; K Grade: fCLKIN = 6 MHz (0ⴗC to 85ⴗC), fSAMPLE = 285 kHz; A and K Grade: fCLKIN = 5 MHz (to 125ⴗC), fSAMPLE = 238 kHz; (AVDD = DVDD = 5.0 V ⴞ 5%, REFIN/REFOUT = 4.096 V External Reference; SLEEP = Logic High; TA = TMIN to TMAX, unless otherwise noted.
AD7851 Parameter POWER PERFORMANCE AVDD, DVDD IDD Normal Mode4 Sleep Mode5 With External Clock On With External Clock Off Normal Mode Power Dissipation Sleep Mode Power Dissipation With External Clock On With External Clock Off SYSTEM CALIBRATION Offset Calibration Span 6 Gain Calibration Span6 Version A1 Version K1 Unit 4.75/5.25 4.75/5.25 V min/max 17 17 mA max AVDD = DVDD = 4.75 V to 5.25 V. Typically 12 mA. 20 20 µA typ 600 600 µA typ 10 10 µA max 300 300 µA typ 89.25 89.
AD7851 TIMING SPECIFICATIONS1 (AV DD = DVDD = 5.0 V ⴞ 5%; fCLKIN = 6 MHz, TA = TMIN to TMAX, unless otherwise noted.) Descriptions that refer to SCLK↑ (rising) or SCLK↓ (falling) edges are with the POLARITY pin HIGH. For the POLARITY pin LOW, then the opposite edge of SCLK will apply.
AD7851 TYPICAL TIMING DIAGRAMS 1.6mA Figures 2 and 3 show typical read and write timing diagrams. Figure 2 shows the reading and writing after conversion in Interface Modes 2 and 3. To attain the maximum sample rate of 285 kHz in Interface Modes 2 and 3, reading and writing must be performed during conversion. Figure 3 shows the timing diagram for Interface Modes 4 and 5 with sample rate of 285 kHz.
AD7851 ABSOLUTE MAXIMUM RATINGS 1 (TA = 25°C, unless otherwise noted.) AVDD to AGND . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V DVDD to DGND . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V AVDD to DVDD . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V Analog Input Voltage to AGND . . . . . –0.3 V to AVDD + 0.3 V Digital Input Voltage to DGND . . . . –0.3 V to DVDD + 0.3 V Digital Output Voltage to DGND . . . –0.3 V to DVDD + 0.3 V REFIN/REFOUT to AGND . . . .
AD7851 TERMINOLOGY Total Harmonic Distortion Integral Nonlinearity Total harmonic distortion (THD) is the ratio of the rms sum of harmonics to the fundamental. For the AD7851, it is defined as This is the maximum deviation from a straight line passing through the endpoints of the ADC transfer function. The endpoints of the transfer function are zero scale, a point 1/2 LSB below the first code transition, and full scale, a point 1/2 LSB above the last code transition.
AD7851 PIN FUNCTION DESCRIPTIONS Pin No. Mnemonic Description 1 CONVST Convert Start. Logic input. A low-to-high transition on this input puts the track-and-hold into its hold mode and starts conversion. When this input is not used, it should be tied to DVDD. 2 BUSY Busy Output. The busy output is triggered high by the falling edge of CONVST or rising edge of CAL and remains high until conversion is completed.
AD7851 AD7851 ON-CHIP REGISTERS The AD7851 powers up with a set of default conditions, and the user need not ever write to the device. In this case, the AD7851 will operate as a read-only ADC. The AD7851 still retains the flexibility for performing a full power-down and a full self-calibration. Note that the DIN pin should be tied to DGND for operating the AD7851 as a read-only ADC.
AD7851 CONTROL REGISTER The arrangement of the control register is shown below. The control register is a write-only register and contains 14 bits of data. The control register is selected by putting two 1s in ADDR1 and ADDR0. The function of the bits in the control register are described below. The power-up status of all bits is 0. MSB ZERO ZERO ZERO ZERO PMGT1 PMGT0 RDSLT1 RDSLT0 2/3 MODE CONVST CALMD CALSLT1 CALSLT0 STCAL LSB Control Register Bit Function Descriptions Bit No.
AD7851 STATUS REGISTER The arrangement of the status register is shown below. The status register is a read-only register and contains 16 bits of data. The status register is selected by first writing to the control register and putting two 1s in RDSLT1 and RDSLT0. The function of the bits in the status register is described below. The power-up status of all bits is 0. START WRITE TO CONTROL REGISTER SETTING RDSLT0 = RDSLT1 = 1 READ STATUS REGISTER Figure 6.
AD7851 CALIBRATION REGISTERS The AD7851 has 10 calibration registers in all, 8 for the DAC, 1 for the offset, and 1 for gain. Data can be written to or read from all 10 calibration registers. In self- and system calibration, the part automatically modifies the calibration registers; only if the user needs to modify the calibration registers should an attempt be made to read from and write to the calibration registers.
AD7851 This gives a resolution of ± 0.0006% of VREF approximately. More accurately the resolution is ± (0.05 × VREF)/213 V = ± 0.015 mV, with a 2.5 V reference. The maximum offset that can be compensated for is ± 5% of the reference voltage, which equates to ± 125 mV with a 2.5 V reference and ± 250 mV with a 5 V reference. START WRITE TO CONTROL REGISTER SETTING STCAL = 0, RDSLT1 = 1, RDSLT0 = 0, AND CALSLT1, CALSLT0 = 00, 01, 10, 11 CAL REGISTER POINTER IS AUTOMATICALLY RESET Q.
AD7851 CIRCUIT INFORMATION The AD7851 is a fast, 14-bit single-supply ADC. The part requires an external 6/7 MHz master clock (CLKIN), two CREF capacitors, a CONVST signal to start conversion, and power supply decoupling capacitors. The part provides the user with track-and-hold, on-chip reference, calibration features, ADC, and serial interface logic functions on a single chip. The ADC section of the AD7851 consists of a conventional successive approximation converter based around a capacitor DAC.
AD7851 The equivalent circuit of the analog input section is shown in Figure 11. During the acquisition interval, the switches are both in the track position and the AIN(+) charges the 20 pF capacitor through the 125 Ω resistance. On the rising edge of CONVST, Switches SW1 and SW2 go into the hold position retaining charge on the 20 pF capacitor as a sample of the signal on AIN(+). The AIN(–) is connected to the 20 pF capacitor, and this unbalances the voltage at Node A at the input of the comparator.
AD7851 Input Ranges Transfer Functions The analog input range for the AD7851 is 0 V to VREF in both the unipolar and bipolar ranges. For the unipolar range, the designed code transitions occur midway between successive integer LSB values (i.e., 1/2 LSB, 3/2 LSBs, 5/2 LSBs . . . FS –3/2 LSBs). The output coding is straight binary for the unipolar range with 1 LSB = FS/16384 = 4.096 V/16384 = 0.25 mV when VREF = 4.096 V.
AD7851 REFERENCE SECTION AD7851 PERFORMANCE CURVES For specified performance, it is recommended that when using an external reference this reference should be between 4 V and the analog supply AVDD. The connections for the relevant reference pins are shown in the typical connection diagrams. If the internal reference is being used, the REFIN/REFOUT pin should have a 100 nF capacitor connected to AGND very close to the REFIN/REFOUT pin. These connections are shown in Figure 18.
AD7851 –72 –74 –76 When using the SLEEP pin, the power management bits PMGT1 and PMGT0 should be set to 0 (default status on power-up). Bringing the SLEEP pin logic high ensures normal operation, and the part does not power down at any stage. This may be necessary if the part is being used at high throughput rates when it is not possible to power down between conversions.
AD7851 When using the on-chip reference and powering up when AVDD and DVDD are first connected, it is recommended that the power-up calibration mode be disabled as explained previously. When using the on-chip reference, the power-up time is effectively the time it takes to charge up the external capacitor on the REFIN /REFOUT pin.
AD7851 Table VII. Power Consumption vs. Throughput Table VIII. Calibration Times (AD7851 with 6 MHz CLKIN) Throughput Rate Power AD7851 Type of Self- or System Calibration Time (ms) 1 kSPS 2 kSPS 9 mW 18 mW Full Gain + Offset Offset Gain 41.7 9.26 4.63 4.63 100 Automatic Calibration on Power-On POWER (mW) 10 1 0.1 0.01 0 200 400 600 800 1000 1200 1400 1600 1800 2000 THROUGHPUT RATE (Hz) Figure 26. Power vs.
AD7851 Self-Calibration Timing MAX SYSTEM FULL SCALE IS ±2.5% FROM VREF Figure 27 shows the timing for a full self-calibration. Here the BUSY line stays high for the full length of the self-calibration. A self-calibration is initiated by bringing the CAL pin low (which initiates an internal reset) and then high again or by writing to the control register and setting the STCAL bit to 1 (note that if the part is in a power-down mode, the CAL pulse width must take account of the power-up time).
AD7851 System Gain and Offset Interaction The inherent architecture of the AD7851 leads to an interaction between the system offset and gain errors when a system calibration is performed. Therefore, it is recommended to perform the cycle of a system offset calibration followed by a system gain calibration twice. Separate system offset and system gain calibrations reduce the offset and gain errors to at least the 14-bit level.
AD7851 SERIAL INTERFACE SUMMARY SM1 and SM2. Interface Mode 1 may only be set by programming the control register (see the Control Register section). External SCLK and SYNC signals (SYNC may be hardwired low) are required for Interfaces Modes 1, 2, and 3. In Interface Modes 4 and 5, the AD7851 generates the SCLK and SYNC. Table IX details the five interface modes and the serial clock edges from which the data is clocked out by the AD7851 (DOUT edge) and that the data is latched in on (DIN edge).
AD7851 DETAILED TIMING SECTION Mode 1 (2-Wire 8051 Interface) The read and writing takes place on the DIN line and the conversion is initiated by pulsing the CONVST pin (note that in every write cycle the 2/3 MODE bit must be set to 1). The conversion may be started by setting the CONVST bit in the control register to 1 instead of using the CONVST line. Below in Figure 33 and in Figure 34 are the timing diagrams for Interface Mode 1 in the 2-wire interface mode.
AD7851 Mode 2 (3-Wire SPI/QSPI Interface Mode) Default Interface Mode Mode 3 (QSPI Interface Mode) Figure 36 shows the timing diagram for Interface Mode 3. In this mode, the DSP is the master and the part is the slave. Here the SYNC input is edge triggered from high to low, and the 16 clock pulses are counted from this edge. Because the clock pulses are counted internally, the SYNC signal does not have to go high after the 16th SCLK rising edge as shown by the dotted SYNC line.
AD7851 this time, the conversion will be complete, the SYNC will go high, and the BUSY will go low. The next falling edge of the CONVST must occur at least 330 ns after the falling edge of BUSY to allow the track-and-hold amplifier adequate acquisition time as shown in Figure 38. This gives a throughput time of 3.68 µs. The maximum throughput rate in this case is 272 kHz. MODE 4 and 5 (Self-Clocking Modes) The timing diagrams in Figure 38 and Figure 39 are for Interface Modes 4 and 5.
AD7851 If the user has control of the CONVST pin but does not want to exercise it for every conversion, the control register may be used to start a conversion. Setting the CONVST bit in the control register to 1 starts a conversion. If the user does not have control of the CONVST pin, a conversion should not be initiated by writing to the control register. The reason for this is that the user may get locked out and not be able to perform any further write/read operations.
AD7851 Writing to the AD7851 For accessing the on-chip registers, it is necessary to write to the part. To enable Serial Interface Mode 1, the user must also write to the part. Figures 41, 42, and 43 shows how to configure the AD7851 for each of the different serial interface modes. The continuous loops on all diagrams indicate the sequence for more than one conversion.
AD7851 Interface Mode 1 Configuration Interface Modes 4 and 5 Configuration Figure 42 shows the flowchart for configuring the part in Interface Mode 1. This mode of operation can only be enabled by writing to the control register and setting the 2/3 MODE bit. Reading and writing cannot take place simultaneously in this mode as the DIN pin is used for both reading and writing. Figure 43 shows the flowchart for configuring the AD7851 in Interface Modes 4 and 5, the self-clocking modes.
AD7851 MICROPROCESSOR INTERFACING OPTIONAL In many applications, the user may not require the facility of writing to the on-chip registers. The user may just want to hardwire the relevant pins to the appropriate levels and read the conversion result. In this case, the DIN pin can be tied low so that the on-chip registers are never used.
AD7851 AD7851 to ADSP-21xx Interface Figure 47 shows the AD7851 interface to the ADSP-21xx. The ADSP-21xx is the slave and the AD7851 is the master. The AD7851 is in Interface Mode 5.
AD7851 APPLICATION HINTS Grounding and Layout Evaluating the AD7851 Performance The analog and digital supplies to the AD7851 are independent and separately pinned out to minimize coupling between the analog and digital sections of the device. The part has very good immunity to noise on the power supplies as can be seen by the PSRR versus frequency graph. However, care should still be taken with regard to grounding and layout.
AD7851 OUTLINE DIMENSIONS 24-Lead Plastic Dual In-Line Package [PDIP] (N-24) Dimensions shown in inches and (millimeters) 1.185 (30.01) 1.165 (29.59) 1.145 (29.08) 24 13 1 12 0.180 (4.57) MAX 0.150 (3.81) 0.130 (3.30) 0.110 (2.79) 0.295 (7.49) 0.285 (7.24) 0.275 (6.99) 0.325 (8.26) 0.310 (7.87) 0.300 (7.62) 0.015 (0.38) MIN 0.022 (0.56) 0.018 (0.46) 0.014 (0.36) 0.100 (2.54) BSC 0.150 (3.81) 0.135 (3.43) 0.120 (3.05) 0.060 (1.52) SEATING 0.050 (1.27) PLANE 0.045 (1.14) 0.015 (0.38) 0.010 (0.
AD7851 24-Lead Shrink Small Outline Package [SSOP] (RS-24) Dimensions shown in millimeters 8.50 8.20 7.90 24 13 5.60 5.30 5.00 1 2.00 MAX 0.05 MIN 0.65 BSC 8.20 7.80 7.40 12 1.85 1.75 1.65 0.10 COPLANARITY 0.38 0.22 SEATING PLANE 0.25 0.09 8ⴗ 4ⴗ 0ⴗ COMPLIANT TO JEDEC STANDARDS MO-150AG REV. B –35– 0.95 0.75 0.
AD7851 Revision History Location Page 3/04—Data Sheet changed from REV. A to REV. B. Updated ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Updated TERMINOLOGY section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Updated PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . . . . . .
