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REV. A

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AD7866

Dual 1 MSPS, 12-Bit, 2-Channel

SAR ADC with Serial Interface

FEATURES

Dual 12-Bit, 2-Channel ADC

Fast Throughput Rate: 1 MSPS

Specified for V

of 2.7 V to 5.25 V

Low Power

11.4 mW Max at 1 MSPS with 3 V Supplies

24 mW Max at 1 MSPS with 5 V Supplies

Wide Input Bandwidth

70 dB SNR at 300 kHz Input Frequency

On-Board Reference 2.5 V

–40ⴗC to +125ⴗC Operation

Flexible Power/Throughput Rate Management

Simultaneous Conversion/Read

No Pipeline Delays

High Speed Serial Interface SPI

/QSPI

MICROWIRE

/DSP Compatible

Shutdown Mode: 1 ␮A Max

20-Lead TSSOP Package

FUNCTIONAL BLOCK DIAGRAM

DGND

OUT

REF SELECT

REF

12-BIT

SUCCESSIVE

APPROXIMATION

ADC

AD7866

2.5V

REF

T/H

MUX

BUF

OUTPUT

DRIVERS

RANGE

SCLK

CONTROL

LOGIC

OUT

12-BIT

SUCCESSIVE

APPROXIMATION

ADC

T/H

MUX

OUTPUT

DRIVERS

BUF

CAP

AAV

CAP

AGND AGND

DRIVE

GENERAL DESCRIPTION

The AD7866 is a dual 12-bit high speed, low power, successive

approximation ADC. The part operates from a single 2.7 V to

5.25 V power supply and features throughput rates up to 1 MSPS.

The device contains two ADCs, each preceded by a low noise,

wide bandwidth track-and-hold amplifier that can handle

input frequencies in excess of 10 MHz.

The conversion process and data acquisition are controlled

using standard control inputs, allowing easy interfacing to

microprocessors or DSPs. The input signal is sampled on the

falling edge of CS; conversion is also initiated at this point.

The conversion time is determined by the SCLK frequency.

There are no pipelined delays associated with the part.

The AD7866 uses advanced design techniques to achieve

very low power dissipation at high throughput rates. With 3 V

supplies and 1 MSPS throughput rate, the part consumes a

maximum of 3.8 mA. With 5 V supplies and 1 MSPS, the

current consumption is a maximum of 4.8 mA. The part also

offers flexible power/throughput rate management when

operating in sleep mode.

The analog input range for the part can be selected to be a 0 V

to V

REF

range or a 2 ⫻ V

REF

range with either straight binary or

twos complement output coding. The AD7866 has an on-chip

2.5 V reference that can be overdriven if an external reference

is preferred. Each on-board ADC can also be supplied with a

separate individual external reference.

The AD7866 is available in a 20-lead thin shrink small outline

(TSSOP) package.

PRODUCT HIGHLIGHTS

1. The AD7866 features two complete ADC functions, allowing

simultaneous sampling and conversion of two channels. Each

ADC has a 2-channel input multiplexer. The conversion result

of both channels is available simultaneously on separate data

lines, or may be taken on one data line if only one serial port

is available.

2. High Throughput with Low Power Consumption—The

AD7866 offers a 1 MSPS throughput rate with 11.4 mW

maximum power consumption when operating at 3 V.

3. Flexible Power/Throughput Rate Management—The conver-

sion rate is determined by the serial clock, allowing the power

consumption to be reduced as the conversion time is reduced

through a SCLK frequency increase. Power efficiency can be

maximized at lower throughput rates if the part enters sleep

during conversions.

4. No Pipeline Delay—The part features two standard successive

approximation ADCs with accurate control of the sampling

instant via a CS input and once off conversion control.

Summary of content (24 pages)

PAGE 1
Dual 1 MSPS, 12-Bit, 2-Channel SAR ADC with Serial Interface AD7866 FEATURES Dual 12-Bit, 2-Channel ADC Fast Throughput Rate: 1 MSPS Specified for VDD of 2.7 V to 5.25 V Low Power 11.4 mW Max at 1 MSPS with 3 V Supplies 24 mW Max at 1 MSPS with 5 V Supplies Wide Input Bandwidth 70 dB SNR at 300 kHz Input Frequency On-Board Reference 2.
PAGE 2
= T to T on D AD7866–SPECIFICATIONS (TExternal A MIN MAX, CAPA Parameter DYNAMIC PERFORMANCE Signal to Noise + Distortion (SINAD) 2 Total Harmonic Distortion (THD) 2 Peak Harmonic or Spurious Noise (SFDR) 2 Intermodulation Distortion (IMD) 2 Second Order Terms Third Order Terms Channel-to-Channel Isolation SAMPLE AND HOLD Aperture Delay3 Aperture Jitter3 Aperture Delay Matching3 Full Power Bandwidth DC ACCURACY Resolution Integral Nonlinearity Differential Nonlinearity 0 V to VREF Input Range Offset Err
PAGE 3
AD7866 Parameter A Version1 B Version1 Unit Test Conditions/Comments CONVERSION RATE Conversion Time Track/Hold Acquisition Time3 Throughput Rate 16 300 1 16 300 1 SCLK cycles ns max MSPS max 800 ns with SCLK = 20 MHz 2.7/5.25 2.7/5.25 2.7/5.25 2.7/5.25 V min/max V min/max 3.1 3.1 mA max 2.8 2.8 mA max 4.8 4.8 mA max 3.8 3.8 mA max Partial Power-Down Mode 1.6 1.
PAGE 4
AD7866 TIMING SPECIFICATIONS1 (V Parameter fSCLK 2 DD = 2.7 V to 5.25 V, VDRIVE = 2.7 V to 5.25 V, VREF = 2.5 V; TA = TMIN to TMAX, unless otherwise noted.
PAGE 5
AD7866 ABSOLUTE MAXIMUM RATINGS 1 Storage Temperature Range . . . . . . . . . . . . –65 C to +150 C Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150 C TSSOP Package, Power Dissipation . . . . . . . . . . . . . 450 mW JA Thermal Impedance (TSSOP) . . . . . . . . . . . . . 143 C/W JC Thermal Impedance (TSSOP) . . . . . . . . . . . . . . 45 C/W Lead Temperature, Soldering Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . . 215 C Infrared (15 sec) . . . . . . .
PAGE 6
AD7866 PIN CONFIGURATION REF SELECT 1 20 A0 DCAPB 2 19 CS AGND 3 18 SCLK 17 VDRIVE VB2 4 VB1 5 AD7866 16 DOUTB TOP VIEW 15 D OUTA (Not to Scale) VA1 7 14 DGND VA2 6 AGND 8 13 DVDD DCAPA 9 12 AVDD VREF 10 11 RANGE PIN FUNCTION DESCRIPTIONS Pin No. Mnemonic Function 1 REF SELECT Internal/External Reference Selection. Logic input. If this pin is tied to GND, the on-chip 2.5 V reference is used as the reference source for both ADC A and ADC B.
PAGE 7
AD7866 PIN FUNCTION DESCRIPTIONS (continued) Pin No. Mnemonic Function 11 RANGE Analog Input Range and Output Coding Selection. Logic input. The polarity on this pin will determine what input range the analog input channels on the AD7866 will have, and will also select the type of output coding the ADC will use for the conversion result. On the falling edge of CS, the polarity of this pin is checked to determine the analog input range of the next conversion.
PAGE 8
AD7866 the fundamental. Noise is the sum of all nonfundamental signals up to half the sampling frequency (fS/2), excluding dc. The ratio is dependent on the number of quantization levels in the digitization process; the more levels, the smaller the quantization noise.
PAGE 9
AD7866 Pf = power at frequency f in ADC output, and PfS = power at frequency fS coupled onto the ADC AVDD supply. Here, a 100 mV peak-to-peak sine wave is coupled onto the AVDD supply while the digital supply is left unaltered. TPCs 3a and 3b show the PSRR of the AD7866 when there is no decoupling on the supply, while TPCs 4a and 4b show the PSRR with decoupling capacitors of 10 µF and 0.1 µF on the supply.
PAGE 10
AD7866 1.0 0 100mV p-p SINE WAVE ON AVDD 2.5V EXT REFERENCE ON VREF TA = 25ⴗC –10 0.6 –30 0.4 –40 0.2 INL – LSB PSRR – dB –20 0.8 –50 –60 0.0 –0.2 VDD = 2.7V –0.4 –70 –0.6 –80 VDD = 3.6V –90 –0.8 –1.0 –100 10k 100k AVDD RIPPLE FREQUENCY – Hz 1k 0 1M 500 1500 2000 2500 ADC – Code 3000 3500 4000 TPC 6. DC INL Plot TPC 4a. PSRR vs. Supply Ripple Frequency, with Supply Decoupling –60 0 –20 RIN = 100⍀ TA = 25ⴗC VDD = 4.75V 100mV p-p SINE WAVE ON AVDD 2.
PAGE 11
AD7866 CIRCUIT INFORMATION CAPACITIVE DAC The AD7866 is a fast, micropower, dual 12-bit, single supply, A/D converter that operates from a 2.7 V to 5.25 V supply. When operated from either a 5 V supply or a 3 V supply, the AD7866 is capable of throughput rates of 1 MSPS when provided with a 20 MHz clock.
PAGE 12
AD7866 Analog Input Ranges The analog input range for the AD7866 can be selected to be 0 V to VREF or 2 VREF with either straight binary or twos complement output coding. The RANGE pin is used to select both the analog input range and the output coding, as shown in Figures 5 to 8. On the falling edge of CS, point A, the logic level of the RANGE pin is checked to determine the analog input range of the next conversion.
PAGE 13
AD7866 A B CS V /2 ⴞ V REF /2 REF INPUT RANGE 1 8 16 1 16 SCLK RANGE DOUTA TWOS COMPLEMENT DOUTB Figure 7. Selecting VREF/2 ± VREF/2 Input Range with Twos Complement Output Coding A B CS 0V TO 2 ⴛ V REF INPUT RANGE 1 8 16 1 16 SCLK RANGE DOUTA STRAIGHT BINARY DOUTB Figure 8.
PAGE 14
AD7866 Digital Inputs The digital inputs applied to the AD7866 are not limited by the maximum ratings that limit the analog inputs. Instead, the digital inputs applied can go to 7 V and are not restricted by the VDD + 0.3 V limit as on the analog inputs. See maximum ratings. 470nF DCAPA AD7866 470nF Another advantage of SCLK, RANGE, REF SELECT, A0, and CS not being restricted by the VDD + 0.3 V limit is that power supply sequencing issues are avoided.
PAGE 15
AD7866 EXT REF 100nF Normal Mode EXT REF VREF DCAPA This mode is intended for fastest throughput rate performance since the user does not have to worry about any power-up times with the AD7866 remaining fully powered all the time. Figure 16 shows the general diagram of the operation of the AD7866 in this mode. 470nF ADC A 2.5V REF BUF A The conversion is initiated on the falling edge of CS, as described in the Serial Interface section.
PAGE 16
AD7866 terminated, and DOUTA and DOUTB will go back into threestate. If CS is brought high before the second SCLK falling edge, the part will remain in normal mode and will not power down. This will avoid accidental power-down due to glitches on the CS line. To exit this mode of operation and power up the AD7866 again, a dummy conversion is performed.
PAGE 17
AD7866 Then, to place the AD7866 in normal mode, a dummy cycle (1 µs to 4 µs approximately) should be initiated. If the first valid conversion is performed directly after the dummy conversion, care must be taken to ensure that adequate acquisition time has been allowed. As mentioned earlier, when powering up from the power-down mode, the part will return to track upon the first SCLK edge applied after the falling edge of CS.
PAGE 18
AD7866 can be said to dissipate 24 mW for 2 µs during each conversion cycle. For the remainder of the conversion cycle, 8 µs, the part remains in partial power-down mode. The AD7866 can be said to dissipate 2.8 mW for the remaining 8 µs of the conversion cycle. If the throughput rate is 100 kSPS, the cycle time is 10 µs and the average power dissipated during each cycle is (2/10) (24 mW) + (8/10) (2.8 mW) = 7.04 mW.
PAGE 19
AD7866 Table III. STATUS Bit Description Bit Bit Name Comment 15 14 ZERO RANGE Leading Zero. This bit will always be a zero output. The polarity of this bit reflects the analog input range that has been selected with the RANGE pin. If it is a 0, it means that in the previous transfer upon the falling edge of the CS, the range pin was at a logic low, providing an analog input range from 0 V to VREF for this conversion.
PAGE 20
AD7866 For example, if the ADSP-2189 had a 20 MHz crystal such that it had a master clock frequency of 40 MHz, then the master cycle time would be 25 ns. If the SCLKDIV register is loaded with the value 3, an SCLK of 5 MHz is obtained and eight master clock periods will elapse for every 1 SCLK period. Depending on the throughput rate selected, if the timer register were loaded with the value, 803, (803 + 1 = 804), for example, 100.
PAGE 21
AD7866 etch technique is generally best for ground planes because it gives the best shielding. Both AGND pins of the AD7866 should be sunk in the AGND plane. Digital and analog ground planes should be joined at only one place. If the AD7866 is in a system where multiple devices require an AGND to DGND connection, the connection should still be made at one point only, a star ground point that should be established as close as possible to the AD7866.
PAGE 22
AD7866 OUTLINE DIMENSIONS 20-Lead Thin Shrink Small Outline Package [TSSOP] (RU-20) Dimensions shown in millimeters 6.60 6.50 6.40 20 11 4.50 4.40 4.30 1 6.40 BSC 10 PIN 1 0.65 BSC 0.15 0.05 0.30 COPLANARITY 0.19 0.10 1.20 MAX 0.20 0.09 SEATING PLANE 8ⴗ 0ⴗ 0.75 0.60 0.45 COMPLIANT TO JEDEC STANDARDS MO-153AC –22– REV.
PAGE 23
AD7866 Revision History Location Page 2/03—Data Sheet changed from REV. 0 to REV. A. Addition to FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Addition to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Changes to ABSOLUTE MAXIMUM RATINGS . . . . . . . . . .
PAGE 24
–24– PRINTED IN U.S.A.