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MOS

Complete, 14-Bit Analog I/O System

AD7869

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

World Wide Web Site: http://www.analog.com

FUNCTIONAL BLOCK DIAGRAM

RO DAC

RI DAC

DGND

AD7869

RO ADC

AGND

CLOCK

14 - BIT

DAC

SERIAL

INTERFACE

ADC SERIAL

INTERFACE

14 - BIT

ADC

DAC 3V

REFERENCE

ADC 3V

REFERENCE

TRACK/HOLD

OUT

LDAC

TFS

TCLK

CONTROL

RFS

RCLK

CLK

CONVST

FEATURES

Complete 14-Bit l/O System, Comprising

14-Bit ADC with Track/Hold Amplifier

83 kHz Throughput Rate

14-Bit DAC with Output Amplifier

3.5 ms Settling Time

On-Chip Voltage Reference

Operates from 65 V Supplies

Low Power—130 mW typ

Small 0.3" Wide DIP

APPLICATIONS

Digital Signal Processing

Speech Recognition and Synthesis

Spectrum Analysis

High Speed Modems

DSP Servo Control

GENERAL DESCRIPTION

The AD7869 is a complete 14-bit I/O system containing a DAC

and an ADC. The ADC is a successive approximation type with

a track-and-hold amplifier, having a combined throughput rate

of 83 kHz. The DAC has an output buffer amplifier with a set-

tling time of 4 µs to 14 bits. Temperature compensated 3 V bur-

ied Zener references provide precision references for the DAC

and ADC.

Interfacing to both the DAC and ADC is serial, minimizing pin

count and giving a small 24-pin package size. Standard control

signals allow serial interfacing to most DSP machines.

Asynchronous ADC conversion control and DAC updating is

made possible with the

CONVST and LDAC logic inputs.

The AD7869 operates from ±5 V power supplies; the analog in-

put/output range of the ADC/DAC is ±3 V. The part is fully

specified for dynamic parameters such as signal-to-noise ratio

and harmonic distortion as well as traditional dc specifications.

The part is available in a 24-pin, 0.3 inch wide, plastic or her-

metic dual-in-line package (DIP) and in a 28-pin, plastic SOIC

package.

PRODUCT HIGHLIGHTS

1. Complete 14-Bit I/O System.

The AD7869 contains a 14-bit ADC with a track-and-hold

amplifier and a 14-bit DAC with output amplifier. Also in

cluded are separate on-chip voltage references for the DAC

and the ADC.

2. Dynamic Specifications for DSP Users.

In addition to traditional dc specifications, the AD7869 is

specified for ac parameters, including signal-to-noise ratio

and harmonic distortion. These parameters, along with im-

portant timing parameters, are tested on every device.

3. Small Package.

The AD7869 is available in a 24-pin DIP and a 28-pin SOIC

package.

REV. B

Tel: 781.329.4700

Fax: 781.461.3113

Summary of content (16 pages)

PAGE 1
a LC2MOS Complete, 14-Bit Analog I/O System AD7869 FEATURES Complete 14-Bit l/O System, Comprising 14-Bit ADC with Track/Hold Amplifier 83 kHz Throughput Rate 14-Bit DAC with Output Amplifier 3.5 ms Settling Time On-Chip Voltage Reference Operates from 65 V Supplies Low Power—130 mW typ Small 0.
PAGE 2
AD7869–SPECIFICATIONS ADC SECTION (VDD = +5 V 6 5%, VSS = –5 V 6 5%, AGND = DGND = 0 V, fCLK = 2.0 MHz external. All specifications TMIN to TMAX unless otherwise noted.
PAGE 3
AD7869 DAC SECTION (VDD = +5 V 6 5%, VSS = –5 V 6 5%, AGND = DGND = 0 V, Rl DAC = +3 V and decoupled as shown in Figure 2, VOUT Load to AGND; = 2 kV, CL = 100 pF. All specifications TMIN to TMAX unless otherwise noted.
PAGE 4
AD7869 TIMING SPECIFICATIONS1, 2 (V DD Parameter ADC TIMING t1 t2 3 t3 t4 t5 4 t6 t135 DAC TIMING t7 t8 t9 t10 t11 tl2 Limit at TMIN, TMAX (All Versions) = +5 V 6 5%, VSS = –5 V 6 5%, AGND = DGND = 0 V) Units Conditions/Comments 50 440 100 20 100 155 4 100 2 RCLK + 200 to 3 RCLK + 200 ns min ns min ns min ns min ns max ns max ns min ns max ns typ CONVST Pulse Width RCLK Cycle Time, Internal Clock RFS to RCLK Falling Edge Setup Time RCLK Rising Edge to RFS 50 75 150 30 75 40 ns min ns min ns min ns
PAGE 5
AD7869 AD7869 PIN FUNCTION DESCRIPTION DIP Pin Number Mnemonic POWER SUPPLY 7 & 23 VDD 10 & 22 VSS 8 & 19 AGND 6 & 17 DGND Function Positive Power Supply, 5 V ± 5%. Both VDD pins must be tied together. Negative Power Supply, –5 V ± 5%. Both VSS pins must be tied together. Analog Ground. Both AGND pins must be tied together. Digital Ground. Both DGND pins must be tied together. ANALOG SIGNAL AND REFERENCE 21 VIN ADC Analog Input. The ADC input range is ± 3 V. Analog Output Voltage from DAC.
PAGE 6
AD7869 CONVERTER DETAILS The AD7869 is a complete 14-bit I/O port; the only external components required for normal operation are pull-up resistors for the ADC data outputs, and power supply decoupling capacitors. The AD7869 is comprised of a 14-bit successive approximation ADC with a track/hold amplifier, a 14-bit DAC with a buffered output and two 3 V buried Zener references, a clock oscillator and control logic.
PAGE 7
AD7869 ADC ADJUSTMENT 500 Figure 6 has signal conditioning at the input and output of the AD7869 for trimming the endpoints of the transfer functions of both the ADC and the DAC. Offset error must be adjusted before full-scale error. For the ADC, this is achieved by trimming the offset of A1 while the input voltage, V1, is 1/2 LSB below ground.
PAGE 8
AD7869 TIMING AND CONTROL DAC TIMING Communication with the AD7869 is managed by six dedicated pins. These consist of separate serial clocks, word framing or strobe pulses, and data signals for both receiving and transmitting data. Conversion starts and DAC updating are controlled by two digital inputs, CONVST and LDAC. These inputs can be asserted independently of the microprocessor by an external timer when precise sampling intervals are required.
PAGE 9
AD7869 AD7869 DYNAMIC SPECIFICATIONS The AD7869 is specified and 100% tested for dynamic performance specifications as well as traditional dc specifications such as Integral and Differential Nonlinearity. These ac specifications are required for signal processing applications such as speech recognition, spectrum analysis and high speed modems. These applications require information on the converter’s effect on the spectral content of the input signal.
PAGE 10
AD7869 The digitizer sampling is synchronized with the DAC update rate to ease FFT calculations. The digitizer samples the DAC output after the output has settled to its new value. Therefore, if the digitizer were to directly sample the output, it would effectively be sampling a dc value each time. As a result, the dynamic performance of the DAC would not be measured correctly. Using the digitizer directly on the DAC output would give better results than the actual performance of the DAC.
PAGE 11
AD7869 MICROPROCESSOR INTERFACING AD7869–DSP56000 Interface Microprocessor interfacing to the AD7869 is via a serial bus that uses standard protocol compatible with DSP machines. The communication interface consists of separate transmit (DAC) and receive (ADC) sections whose operations can be either synchronous or asynchronous with respect to each other. Each section has a clock signal, a data signal and a frame or strobe pulse.
PAGE 12
AD7869 AD7869–TMS32020 Interface Figure 18 shows an interface that is suitable for the TMS32020/ TMS320C25 processors. This interface is configured for synchronous, continuous clock operation. Note the AD7869 will not correctly interface to these processors if the AD7869 is configured for a noncontinuous clock. Conversion starts and DAC updating are controlled by an external timer. TIMER CONTROL + 5V AD7869* 2kΩ FSR CLKR 4.
PAGE 13
AD7869 5V V+ IN OUT C2 0.1µF IC5 78L05 V+ C1 10µF GND C5 10µF ANALOG INPUT ±3V RANGE C6 0.1µF V DD LK1 A B + SKT1 R7 200 RO ADC V IN IC2 C V DD AD711 COMPONENT GRID RI DAC C7 10µF C8 0.1µF C24 0.1µF A B V– LK4 C RO DAC IC1 AD7869 – 5V A B LK5 CONTROL C COMPONENT GRID LK2 AGND SKT6 9-WAY D-TYPE CONNECTOR B C AGND SKT2 B 5V A A C ANALOG OUTPUT ±3V RANGE C23 10µF DGND R3 4.7k Ω LK3 V+ DGND C10 0.1µF R4 2k Ω IC7 1/2 74HC4050 R5 4.
PAGE 14
AD7869 COMPONENT LIST C21 C22 330 pF Capacitor 68 pF Capacitor R1, R2, R4 R3, R5 R6 R7 2 kΩ Resistor 4.7 kΩ Resistor 15 kΩ Resistor 200 Ω Resistor 10 µF Capacitor LK1, LK2, LK3, LK4, LK5, LK6, LK7, LK8, LK9 SKT1, SKT2, SKT3, SKT4, SKT5 Shorting Plugs BNC Sockets 0.
PAGE 15
AD7869 Figure 22. Component Side Layout for the Circuit Diagram of Figure 19 Figure 23. Solder Side Layout for the Circuit Diagram of Figure 19 REV.
PAGE 16
AD7869 Outline Dimensions 1.280 (32.51) 1.250 (31.75) 1.230 (31.24) 24 13 1 12 0.280 (7.11) 0.250 (6.35) 0.240 (6.10) 0.325 (8.26) 0.310 (7.87) 0.300 (7.62) 0.100 (2.54) BSC 0.060 (1.52) MAX 0.210 (5.33) MAX 0.195 (4.95) 0.130 (3.30) 0.115 (2.92) 0.015 (0.38) MIN 0.150 (3.81) 0.130 (3.30) 0.115 (2.92) 0.015 (0.38) GAUGE PLANE SEATING PLANE 0.022 (0.56) 0.018 (0.46) 0.014 (0.36) 0.014 (0.36) 0.010 (0.25) 0.008 (0.20) 0.430 (10.92) MAX 0.005 (0.13) MIN 0.070 (1.78) 0.060 (1.52) 0.045 (1.