Datasheet

ManualsBrandsANALOG DEVICES ManualsData collecting ICsData acquisition IC - AD converter (ADC) External SOIC 8

FUNCTIONAL BLOCK DIAGRAM

AGND

DGND SCLK

CONVST

AD7893

SDATA

REF IN

TRACK/

HOLD

*AD7893-5, AD7893-10, AD7893-3

SIGNAL

SCALING*

12-BIT

ADC

OUTPUT

REV. E

Information furnished by Analog Devices is believed to be accurate and

reliable. However, no responsibility is assumed by Analog Devices for its

use, nor for any infringements of patents or other rights of third parties

which may result from its use. No license is granted by implication or

otherwise under any patent or patent rights of Analog Devices.

MOS 12-Bit, Serial 6 ms

ADC in 8-Pin Package

AD7893

FEATURES

Fast 12-Bit ADC with 6 ms Conversion Time

8-Pin Mini-DlP and SOIC

Single Supply Operation

High Speed, Easy-to-Use, Serial Interface

On-Chip Track/Hold Amplifier

Selection of Input Ranges

610 V for AD7893-10

62.5 V for AD7893-3

0 V to +2.5 V for AD7893-2

0 V to +5 V for AD7893-5

Low Power: 25 mW typ

GENERAL DESCRIPTION

The AD7893 is a fast, 12-bit ADC that operates from a single

+5 V supply and is housed in a small 8-pin mini-DIP and 8-pin

SOIC. The part contains a 6 µs successive approximation A/D

converter, an on-chip track/hold amplifier, an on-chip clock and

a high speed serial interface.

Output data from the AD7893 is provided via a high speed,

serial interface port. This two-wire serial interface has a serial

clock input and a serial data output with the external serial clock

accessing the serial data from the part.

In addition to traditional dc accuracy specifications such as lin-

earity, full-scale and offset errors, the AD7893 is also specified

for dynamic performance parameters, including harmonic dis-

tortion and signal-to-noise ratio.

The part accepts an analog input range of ±10 V (AD7893-10),

±2.5 V (AD7893-3), 0 V to +5 V (AD7893-5) or 0 V to +2.5 V

(AD7893-2) and operates from a single +5 V supply, consuming

only 25 mW typical.

The AD7893 is fabricated in Analog Devices’ Linear Compat-

ible CMOS (LC

MOS) process, a mixed technology process

that combines precision bipolar circuits with low power CMOS

logic. The part is available in a small, 8-pin, 0.3" wide, plastic or

hermetic dual-in-line package (mini-DIP) and in an 8-pin, small

outline IC (SOIC).

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 617/329-4700 World Wide Web Site: http://www.analog.com

PRODUCT HIGHLIGHTS

1. Fast, 12-Bit ADC in 8-Pin Package

The AD7893 contains a 6 µs ADC, a track/hold amplifier,

control logic and a high speed serial interface, all in an 8-pin

package. This offers considerable space saving over alterna-

tive solutions.

2. Low Power, Single Supply Operation

The AD7893 operates from a single +5 V supply and con-

sumes only 25 mW. This low power, single supply operation

makes it ideal for battery powered or portable applications.

3. High Speed Serial Interface

The part provides high speed serial data and serial clock lines,

allowing for an easy, two-wire serial interface arrangement.

Summary of content (12 pages)

PAGE 1
a FEATURES Fast 12-Bit ADC with 6 ms Conversion Time 8-Pin Mini-DlP and SOIC Single Supply Operation High Speed, Easy-to-Use, Serial Interface On-Chip Track/Hold Amplifier Selection of Input Ranges 610 V for AD7893-10 62.5 V for AD7893-3 0 V to +2.
PAGE 2
= +5 V, AGND = DGND = 0 V, REF IN = +2.5 V. All specifications T AD7893–SPECIFICATIONS (Votherwise noted.
PAGE 3
AD7893 TIMING CHARACTERISTICS1, 2 (V Parameter t1 t2 t3 t4 3 t5 4 DD = +5 V, AGND = DGND = 0 V, REF IN = +2.5 V) A, B Versions S Version Units Test Conditions/Comments 50 60 30 50 10 100 50 70 40 60 10 100 ns min ns min ns min ns max ns min ns max CONVST Pulse Width SCLK High Pulse Width SCLK Low Pulse Width SCLK Rising Edge to Data Valid Delay Bus Relinquish Time after Falling Edge of SCLK NOTES 1 Sample tested at +25°C to ensure compliance.
PAGE 4
AD7893 PIN FUNCTION DESCRIPTION Pin No. Pin Mnemonic 1 REF IN Voltage Reference Input. An external reference source should be connected to this pin to provide the reference voltage for the AD7893’s conversion process. The REF IN input is buffered on-chip. The nominal reference voltage for correct operation of the AD7893 is +2.5 V. 2 VIN Analog Input Channel. The analog input range is ± 10 V (AD7893-10), ± 2.5 V (AD7893-3), 0 V to +5 V (AD7893-5) and 0 V to +2.5 V (AD7893-2). 3 AGND Analog Ground.
PAGE 5
AD7893 TERMINOLOGY Signal to (Noise + Distortion) Ratio This is the measured ratio of signal to (noise + distortion) at the output of the A/D converter. The signal is the rms amplitude of the fundamental. Noise is the rms sum of all nonfundamental signals up to half the sampling frequency (fS/2), excluding dc. The ratio is dependent upon the number of quantization levels in the digitization process; the more levels, the smaller the quantization noise.
PAGE 6
AD7893 CONVERTER DETAILS The AD7893 is a fast, 12-bit single supply A/D converter. It provides the user with signal scaling (AD7893-10), track/hold, A/D converter and serial interface logic functions on a single chip. The A/D converter section of the AD7893 consists of a conventional successive-approximation converter based on an R-2R ladder structure. The signal scaling on the AD7893-10, AD7893-5 and AD7893-3 allows the part to handle ± 10 V, 0 V to +5 V and ± 2.
PAGE 7
AD7893 Track/Hold Section The track/hold amplifier on the analog input of the AD7893 allows the ADC to accurately convert an input sine wave of fullscale amplitude to 12-bit accuracy. The input bandwidth of the track/hold is greater than the Nyquist rate of the ADC, even when the ADC is operated at its maximum throughput rate of 117 kHz (i.e., the track/hold can handle input frequencies in excess of 58 kHz). The track/hold amplifier acquires an input signal to 12-bit accuracy in less than 1.5 µs.
PAGE 8
AD7893 CONVST 600ns MIN SCLK tCONVERT CONVERSION IS INITIATED AND TRACK/HOLD GOES INTO HOLD CONVST INDICATES TO µP THAT CONVERSION IS COMPLETE µP INT SERVICE OR POLLING ROUTINE SERIAL READ OPERATION READ OPERATION SHOULD END 600ns PRIOR TO NEXT RISING EDGE OF CONVST Figure 4.
PAGE 9
AD7893 The AD7893 counts the serial clock edges to know which bit from the output register should be placed on the SDATA output. To ensure that the part does not lose synchronization, the serial clock counter is reset on the falling edge of the CONVST input, provided the SCLR line is low. The user should ensure that a falling edge on the CONVST input does not occur while a serial data read operation is in progress.
PAGE 10
AD7893 AD7893–ADSP-2105 Interface An interface circuit between the AD7893 and the ADSP-2105 DSP processor is shown in Figure 8. In the interface shown, the RFS1 output from the ADSP-2105’s SPORT1 serial port is used to gate the serial clock (SCLK1) of the ADSP-2105 before it is applied to the SCLK input of the AD7893. The RFS1 output is configured for active high operation.
PAGE 11
AD7893 The same data is presented in Figure 11 as in Figure 10 except that, in this case, the output data read for the device occurs during conversion. This has the effect of injecting noise onto the die while bit decisions are being made; this increases the noise generated by the AD7893. The histogram plot for 8192 conversions of the same dc input now shows a larger spread of codes with the rms noise for the AD7893-2 increasing to 210 µV.
PAGE 12
AD7893 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 8 C1787c–2–1/97 Plastic DIP (N-8) 5 0.280 (7.11) 0.240 (6.10) PIN 1 1 4 0.325 (8.25) 0.300 (7.62) 0.430 (10.92) 0.348 (8.84) 0.060 (1.52) 0.015 (0.38) 0.210 (5.33) MAX 0.130 (3.30) MIN 0.160 (4.06) 0.115 (2.93) 0.100 (2.54) BSC 0.022 (0.558) 0.014 (0.356) 0.070 (1.77) 0.045 (1.15) 0.195 (4.95) 0.115 (2.93) 0.015 (0.381) 0.008 (0.204) SEATING PLANE Cerdip (Q-8) 0.005 (0.13) MIN 0.055 (1.4) MAX 8 5 0.310 (7.87) 0.220 (5.