Datasheet

ManualsBrandsANALOG DEVICES ManualsData collecting ICsData acquisition IC - AD converter (ADC) Supply MSOP 8

3 mW, 100 kSPS,

14-Bit ADC in 6-Lead SOT-23

AD7940

Rev. A

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FEATURES

Fast throughput rate: 100 kSPS

Specified for V

of 2.5 V to 5.5 V

Low power

4 mW typ at 100 kSPS with 3 V supplies

17 mW typ at 100 kSPS with 5 V supplies

Wide input bandwidth:

81 dB SINAD at 10 kHz input frequency

Flexible power/serial clock speed management

No pipeline delays

High speed serial interface

SPI®/QSPI™/MICROWIRE™/DSP compatible

Standby mode: 0.5 µA max

6-Lead SOT-23 and 8-Lead MSOP packages

APPLICATIONS

Battery-powered systems

Personal digital assistants

Medical instruments

Mobile communications

Instrumentation and control systems

Remote data acquisition systems

FUNCTIONAL BLOCK DIAGRAM

03305-0-001

GND

AD7940

SCLK

SDATA

T/H

14-BIT SUCCESSIVE

APPROXIMATION

ADC

CONTROL

LOGIC

Figure 1.

Table 1. 16-Bit and 14-Bit ADC (MSOP and SOT-23)

Type 100 kSPS 250 kSPS 500 kSPS

16-Bit True Differential AD7684 AD7687 AD7688

16-Bit Pseudo Differential AD7683 AD7685 AD7686

16-Bit Unipolar AD7680

14-Bit True Differential AD7944 AD7947

14-Bit Pseudo Differential AD7942 AD7946

14-Bit Unipolar AD7940

GENERAL DESCRIPTION

The AD7940

is a 14-bit, fast, low power, successive

approximation ADC. The part operates from a single 2.50 V to

5.5 V power supply and features throughput rates up to 100 kSPS.

The part contains a low noise, wide bandwidth track-and-hold

amplifier that can handle input frequencies in excess of 7 MHz.

The conversion process and data acquisition are controlled

using

and the serial clock, allowing the devices to interface

with microprocessors or DSPs. The input signal is sampled on

the falling edge of

and the conversion is also initiated at this

point. There are no pipelined delays associated with the part.

The AD7940 uses advanced design techniques to achieve very

low power dissipation at fast throughput rates. The reference for

the part is taken internally from V

, which allows the widest

dynamic input range to the ADC. Thus, the analog input range

for this part is 0 V to V

. The conversion rate is determined by

the SCLK frequency.

Protected by US. Patent No. 6,681,332.

This part features a standard successive approximation ADC

with accurate control of the sampling instant via a

input and

once off conversion control.

PRODUCT HIGHLIGHTS

1. First 14-bit ADC in a SOT-23 package.

2. High throughput with low power consumption.

3. Fl

exible power/serial clock speed management. The

conv

ersion rate is determined by the serial clock, allowing

the conversion time to be reduced through the serial clock

speed increase. This allows the average power consumption

to be reduced when a power-down mode is used while not

converting. The part also features a shutdown mode to

maximize power efficiency at lower throughput rates.

Power consumption is 0.5 µA max when in shutdown.

4. Reference derived from the power suppl

5. No pipeline delay.

Summary of content (20 pages)

PAGE 1
3 mW, 100 kSPS, 14-Bit ADC in 6-Lead SOT-23 AD7940 FUNCTIONAL BLOCK DIAGRAM FEATURES APPLICATIONS Battery-powered systems Personal digital assistants Medical instruments Mobile communications Instrumentation and control systems Remote data acquisition systems GENERAL DESCRIPTION 1 The AD7940 is a 14-bit, fast, low power, successive approximation ADC. The part operates from a single 2.50 V to 5.5 V power supply and features throughput rates up to 100 kSPS.
PAGE 2
AD7940 TABLE OF CONTENTS Table of Contents .............................................................................. 2 Normal Mode.............................................................................. 13 Specifications..................................................................................... 3 Power-Down Mode .................................................................... 14 Timing Specifications.......................................................................
PAGE 3
AD7940 SPECIFICATIONS1 VDD = 2.50 V to 5.5 V, fSCLK = 2.5 MHz, fSAMPLE = 100 kSPS, unless otherwise noted; TA = TMIN to TMAX, unless otherwise noted. Table 2.
PAGE 4
AD7940 Parameter Power Dissipation 4 Normal Mode (Operational) Full Power-Down B Version1 Unit 26.4 6.84 2.5 1.08 mW max mW max µW max µW max 1 Temperature range for B Version is –40°C to +85°C. See the Terminology section. Sample tested at initial release to ensure compliance. 4 See the Power vs. Throughput Rate section. 2 3 Rev. A | Page 4 of 20 Test Conditions/Comments VDD = 5.5 V VDD = 5.5 V; fSAMPLE = 100 kSPS VDD = 3.6 V; fSAMPLE = 100 kSPS VDD = 5.5 V VDD = 3.
PAGE 5
AD7940 TIMING SPECIFICATIONS Sample tested at initial release to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V. VDD = 2.50 V to 5.5 V; TA = TMIN to TMAX, unless otherwise noted. Table 3. tCONVERT tQUIET Limit at TMIN, TMAX 3V 5V 250 250 2.5 2.5 16 × tSCLK 16 × tSCLK 50 50 Unit kHz min MHz max min ns min t1 t2 t3 2 t4 2 t5 t6 t7 t8 3 tPOWER-UP 4 10 10 48 120 0.4 tSCLK 0.
PAGE 6
AD7940 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 4.
PAGE 7
AD7940 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS AD7940 6 CS 5 SDATA TOP VIEW VIN 3 (Not to Scale) 4 SCLK VDD 1 GND 2 03305-0-023 VDD 1 GND 2 AD7490 TOP VIEW GND 3 (Not to Scale) 4 VIN Figure 3. SOT-23 Pin Configuration 8 CS 7 SDATA 6 NC 5 SCLK NC = NO CONNECT 03305-0-003 MSOP SOT-23 Figure 4. MSOP Pin Configuration Table 5. Pin Function Descriptions Pin No. SOT-23 1 2 Pin No.
PAGE 8
AD7940 TERMINOLOGY Integral Nonlinearity This is the maximum deviation from a straight line passing through the endpoints of the ADC transfer function. The endpoints of the transfer function are zero scale, a point 1/2 LSB below the first code transition, and full scale, a point 1/2 LSB above the last code transition. Differential Nonlinearity This is the difference between the measured and the ideal 1 LSB change between any two adjacent codes in the ADC.
PAGE 9
AD7940 TYPICAL PERFORMANCE CHARACTERISTICS Figure 5 shows a typical FFT plot for the AD7940 at 100 kSPS sample rate and 10 kHz input frequency. Figure 6 shows the signal-to-(noise + distortion) ratio performance versus the input frequency for various supply voltages while sampling at 100 kSPS with an SCLK of 2.5 MHz.
PAGE 10
AD7940 0.8 VDD = 3.00V TEMP = 25°C 0.6 0.6 0.4 DNL ERROR (LSB) 0.8 0.4 0.2 0 VDD = 3.00V TEMP = 25°C 0.2 0 –0.2 –0.4 –0.6 0 2000 4000 6000 03305-0-017 –0.4 –0.2 03305-0-018 INL ERROR (LSB) 1.0 –0.6 –0.8 0 8000 10000 12000 14000 16000 18000 2000 4000 6000 8000 10000 12000 14000 16000 18000 CODE CODE Figure 9. AD7940 Typical INL Figure 10. AD7940 Typical DNL Rev.
PAGE 11
AD7940 CIRCUIT INFORMATION The AD7940 provides the user with an on-chip track-and-hold ADC and a serial interface housed in a tiny 6-lead SOT-23 package or in an 8-lead MSOP package, which offer the user considerable space-saving advantages over alternative solutions. The serial clock input accesses data from the part and also provides the clock source for the successive approximation ADC. The analog input range for the AD7940 is 0 V to VDD.
PAGE 12
AD7940 ADC TRANSFER FUNCTION The output coding of the AD7940 is straight binary. The designed code transitions occur at successive integer LSB values, i.e., 1 LSB, 2 LSBs. The LSB size is VDD/16384. The ideal transfer characteristic for the AD7940 is shown in Figure 14. 111...111 111...110 111...000 1 LSB = VDD/16384 011...111 In fact, because the supply current required by the AD7940 is so low, a precision reference can be used as the supply source to the AD7940.
PAGE 13
AD7940 MODES OF OPERATION The mode of operation of the AD7940 is selected by controlling the (logic) state of the CS signal during a conversion. There are two possible modes of operation, normal and power-down. The point at which CS is pulled high after the conversion has been initiated will determine whether or not the AD7940 will enter power-down mode. Similarly, if already in power-down, CS can control whether the device will return to normal operation or remain in power-down.
PAGE 14
AD7940 POWER-DOWN MODE This mode is intended for use in applications where slower throughput rates are required. Either the ADC is powered down between each conversion, or a series of conversions may be performed at a high throughput rate, and then the ADC is powered down for a relatively long duration between these bursts of several conversions. When the AD7940 is in powerdown, all analog circuitry is powered down.
PAGE 15
AD7940 POWER VS. THROUGHPUT RATE Figure 19 shows the power dissipation versus the throughput rate when using the power-down mode with 3.6 V supplies and a 2.5 MHz SCLK. (7.4/100) × (6.84 mW) + (92.6/100) × (1.08 µW) = 0.51 mW Rev. A | Page 15 of 20 VDD = 3.6V FSCLK = 2.5MHz 1 0.1 03305-0-012 For example, if the AD7940 is operated in a continuous sampling mode, with a throughput rate of 10 kSPS and an SCLK of 2.5 MHz (VDD = 3.
PAGE 16
AD7940 SERIAL INTERFACE Figure 20 shows the detailed timing diagram for serial interfacing to the AD7940. The serial clock provides the conversion clock and also controls the transfer of information from the AD7940 during conversion. The CS signal initiates the data transfer and conversion process. The falling edge of CS puts the track-and-hold into hold mode, takes the bus out of three-state, and samples the analog input.
PAGE 17
AD7940 MICROPROCESSOR INTERFACING The serial interface on the AD7940 allows the part to be directly connected to a range of many different microprocessors. This section explains how to interface the AD7940 with some of the more common microcontroller and DSP serial interface protocols. AD7940 TO ADSP-218x The ADSP-218x family of DSPs can be interfaced directly to the AD7940 with no glue logic required.
PAGE 18
AD7940 For example, if the ADSP-2189 had a 20 MHz crystal, such that it had a master clock frequency of 40 MHz, the master cycle time would be 25 ns. If the SCLKDIV register is loaded with the value 7, then a SCLK of 2.5 MHz is obtained, and 16 master clock periods will elapse for every 1 SCLK period. Depending on the throughput rate selected, if the timer register was loaded with the value 803 (803 + 1 = 804), then 50.25 SCLKs will occur between interrupts and subsequently between transmit instructions.
PAGE 19
AD7940 APPLICATION HINTS GROUNDING AND LAYOUT The printed circuit board that houses the AD7940 should be designed such that the analog and digital sections are separated and confined to certain areas of the board. This facilitates the use of ground planes that can be separated easily. A minimum etch technique is generally best for ground planes, since it gives the best shielding. Digital and analog ground planes should be joined at only one place.
PAGE 20
AD7940 OUTLINE DIMENSIONS 3.00 2.90 2.80 1.70 1.60 1.50 6 5 4 1 2 3 3.00 2.80 2.60 PIN 1 INDICATOR 0.95 BSC 1.90 BSC 1.30 1.15 0.90 0.20 MAX 0.08 MIN 0.15 MAX 0.05 MIN 10° 4° 0° SEATING PLANE 0.50 MAX 0.30 MIN 0.60 BSC 0.55 0.45 0.35 12-16-2008-A 1.45 MAX 0.95 MIN COMPLIANT TO JEDEC STANDARDS MO-178-AB Figure 24. 6-Lead Small Outline Transistor Package [SOT-23] (RJ-6). Dimensions shown in millimeters 3.20 3.00 2.80 8 3.20 3.00 2.80 1 5 5.15 4.90 4.65 4 PIN 1 IDENTIFIER 0.65 BSC 0.