Datasheet

ManualsBrandsANALOG DEVICES ManualsData collecting ICsData acquisition IC - AD converter (ADC) External , Internal LFCSP 20 VQ

14-Bit, 2.5 MSPS, PulSAR

15.5 mW ADC in LFCSP

AD7944

Rev. A

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FEATURES

14-bit resolution with no missing codes

Throughput: 2.5 MSPS (TURBO high), 2.0 MSPS (TURBO low)

Low power dissipation

15.5 mW at 2.5 MSPS, with external reference

28 mW at 2.5 MSPS, with internal reference

INL: ±0.25 LSB typical, ±1.0 LSB maximum

SNR

84 dB, with on-chip reference

84.5 dB, with external reference

4.096 V internal reference: typical drift of ±10 ppm/°C

Pseudo differential analog input voltage range

0 V to V

REF

with V

REF

up to 5.0 V

Allows use of any input range

No pipeline delay

Logic interface: 1.8 V/2.5 V/2.7 V

Serial interface: SPI-/QSPI-/MICROWIRE-/DSP-compatible

Ability to daisy-chain multiple ADCs with busy indicator

20-lead, 4 mm × 4 mm LFCSP (QFN)

APPLICATIONS

Battery-powered equipment

Communications

ATE

Data acquisition systems

Medical instruments

APPLICATION DIAGRAM

REF

NOTES

1. GND REFERS TO REFGND, AGND, AND DGND.

AD7944

GND REF

AVDD,

DVDD

VIO

BVDD

5V 2.5V

1.8V

2.7V

VIO

SDI

SCK

SDO

CNV

3- OR 4-WIRE

INTERFACE:

SPI, CS,

DAISY CHAIN

(TURBO = LOW)

TURBO

10µF

IN+

IN–

04658-001

Figure 1.

GENERAL DESCRIPTION

The AD7944 is a 14-bit, 2.5 MSPS successive approximation

analog-to-digital converter (SAR ADC). It contains a low power,

high speed, 14-bit sampling ADC, an internal conversion clock,

an internal reference (and buffer), error correction circuits, and

a versatile serial interface port. On the rising edge of C NV, th e

AD7944 samples an analog input, IN+, between 0 V and V

REF

with respect to a ground sense, IN−. The AD7944 features a

very high sampling rate turbo mode (TURBO high) and a

reduced power normal mode (TURBO low) for low power

applications where the power is scaled with the throughput.

In normal mode (TURBO low), the SPI-compatible serial inter-

face also features the ability, using the SDI input, to daisy-chain

several ADCs on a single 3-wire bus and provide an optional busy

indicator. The serial interface is compatible with 1.8 V, 2.5 V,

and 2.7 V supplies using the separate VIO supply.

The AD7944 is available in a 20-lead LFCSP with operation

specified from −40°C to +85°C.

Table 1. MSOP, LFCSP, 14-/16-/18-Bit PulSAR® ADCs

Type 100 kSPS 250 kSPS 400 kSPS to 500 kSPS ≥1000 kSPS ADC Driver

14-Bit AD7940 AD7942

AD7946

AD7944

16-Bit AD7680 AD7685

AD7686

AD7980

ADA4941-1

AD7683 AD7687

AD7688

AD7983

ADA4841-x

AD7684 AD7694 AD7693

AD7985

AD8021

18-Bit AD7691

AD7690

AD7982

ADA4941-1

AD7984

ADA4841-x

AD7986

AD8021

See www.analog.com for the latest selection of PulSAR ADCs and ADC drivers.

Pin-for-pin compatible with all other parts marked with this endnote.

The AD7944, AD7985, and AD7986 are pin-for-pin compatible.

Summary of content (28 pages)

PAGE 1
4-Bit, 2.5 MSPS, PulSAR 15.5 mW ADC in LFCSP AD7944 FEATURES APPLICATION DIAGRAM 14-bit resolution with no missing codes Throughput: 2.5 MSPS (TURBO high), 2.0 MSPS (TURBO low) Low power dissipation 15.5 mW at 2.5 MSPS, with external reference 28 mW at 2.5 MSPS, with internal reference INL: ±0.25 LSB typical, ±1.0 LSB maximum SNR 84 dB, with on-chip reference 84.5 dB, with external reference 4.
PAGE 2
AD7944 TABLE OF CONTENTS Features .............................................................................................. 1 Analog Inputs.............................................................................. 15 Applications ....................................................................................... 1 Driver Amplifier Choice ........................................................... 15 Application Diagram ........................................................................
PAGE 3
AD7944 SPECIFICATIONS AVDD = DVDD = 2.5 V, BVDD = 5 V, VIO = 1.8 V to 2.7 V, VREF = 4.096 V, TA = −40°C to +85°C, unless otherwise noted. Table 2.
PAGE 4
AD7944 Table 3. Parameter INTERNAL REFERENCE Output Voltage Temperature Drift Line Regulation Turn-On Settling Time REFIN Output Voltage REFIN Output Resistance EXTERNAL REFERENCE Voltage Range Current Drain REFERENCE BUFFER REFIN Input Voltage REFIN Input Current DIGITAL INPUTS Logic Levels VIL VIH IIL IIH DIGITAL OUTPUTS Data Format Pipeline Delay Test Conditions/Comments PDREF is low TA = 25°C −40°C to +85°C AVDD = 2.5 V ± 5% CREF = 10 μF, CREFIN = 0.
PAGE 5
AD7944 TIMING SPECIFICATIONS AVDD = DVDD = 2.5 V, BVDD = 5 V, VIO = 1.8 V to 2.7 V, VREF = 4.096 V, TA = −40°C to +85°C, unless otherwise noted.1 Table 4.
PAGE 6
AD7944 ABSOLUTE MAXIMUM RATINGS Table 5. Parameter Analog Inputs IN+, IN− to GND 1 Supply Voltage REF, BVDD to GND, REFGND AVDD, DVDD, VIO to GND AVDD, DVDD to VIO Digital Inputs to GND Digital Outputs to GND Storage Temperature Range Junction Temperature θJA Thermal Impedance 20-Lead LFCSP (QFN) Lead Temperatures Vapor Phase (60 sec) Infrared (15 sec) 1 Rating −0.3 V to VREF + 0.3 V or ±130 mA −0.3 V to +6.0 V −0.3 V to +2.7 V −6 V to +3 V −0.3 V to VIO + 0.3 V −0.3 V to VIO + 0.
PAGE 7
AD7944 20 19 18 17 16 REFIN BVDD AGND AGND AVDD PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 2 3 4 5 PIN 1 INDICATOR AD7944 TOP VIEW (Not to Scale) 15 TURBO 14 SDI 13 CNV 12 SCK 11 DVDD NOTES 1. THE EXPOSED PAD IS NOT CONNECTED INTERNALLY. FOR INCREASED RELIABILITY OF THE SOLDER JOINTS, IT IS RECOMMENDED THAT THE PAD BE SOLDERED TO THE SYSTEM GROUND PLANE. 04658-004 IN+ PDREF VIO SDO DGND 6 7 8 9 10 REF REF REFGND REFGND IN– Figure 4. Pin Configuration Table 6.
PAGE 8
AD7944 Pin No. 19 Mnemonic BVDD Type1 P 20 REFIN AI/O EP Exposed Pad EP 1 Description Reference Buffer Power. Nominally at 5.0 V. If an external reference buffer is used to achieve the maximum SNR performance with a 5 V reference, the reference buffer must be powered down by connecting the REFIN pin to ground. The external reference buffer must be connected to the BVDD pin. Internal Reference Output/Reference Buffer Input. When PDREF is low, the internal band gap reference produces a 1.
PAGE 9
AD7944 TYPICAL PERFORMANCE CHARACTERISTICS AVDD = DVDD = VIO = 2.5 V, BVDD = 5.0 V, VREF = 5.0 V, external reference (PDREF is high, REFIN is low), unless otherwise noted. 0.8 0.6 0.6 0.4 0.4 0.2 0.2 0 –0.2 0 –0.2 –0.4 –0.4 –0.6 –0.6 –0.8 –0.8 0 4096 8192 12,288 16,384 CODE –1.0 04658-105 –1.0 POSITIVE DNL = +0.11LSB NEGATIVE DNL = –0.11LSB 0.8 DNL (LSB) INL (LSB) 1.0 POSITIVE INL = +0.12 LSB NEGATIVE INL = –0.20 LSB 0 4096 8192 12,288 16,384 CODE 04658-108 1.0 Figure 8.
PAGE 10
AD7944 –40 –40 AMPLITUDE (dB) –60 –80 –100 –120 –60 –80 –100 –120 –140 –140 –160 –160 0 250 500 750 1000 1250 FREQUENCY (kHz) –180 04658-111 –180 fS = 2.5MSPS fIN = 20kHz SNR = 84dB THD = –102dB SINAD = 84dB –20 SNR = 84.65dB THD = –100dB SINAD = 84.5dB 0 250 14.5 –101 81 13.5 ENOB 80 13.0 79 12.5 3.5 4.0 4.5 THD (dB) 14.0 ENOB (Bits) 82 –102 –103 –104 12.0 5.0 –105 2.50 04658-112 SNR, SINAD (dB) SINAD 3.0 1250 –100 15.0 83 2.5 1000 Figure 14.
PAGE 11
AD7944 2.0 89 1.8 88 1.6 OPERATING CURRENT (mA) 90 86 85 84 83 82 81 1.2 1.0 0.8 IREF 0.4 –8 –7 –6 –5 –4 –3 –2 –1 0 0 –55 –35 –15 5 25 45 65 85 105 125 TEMPERATURE (°C) Figure 17. SNR vs. Input Level 04658-119 –9 INPUT LEVEL (dBFS) Figure 19. Operating Current vs. Temperature 14 2.0 1.8 IAVDD 12 1.6 SUPPLY CURRENT (µA) IDVDD 1.4 IVIO 1.2 1.0 0.8 IBVDD 0.6 IREF 10 8 6 4 IAVDD + IDVDD + IVIO 0.4 2 0.2 0 2.375 2.425 2.475 2.525 2.
PAGE 12
AD7944 TERMINOLOGY Aperture Delay Aperture delay is the measure of the acquisition performance. It is the time between the rising edge of the CNV input and when the input signal is held for a conversion. Differential Nonlinearity Error (DNL) In an ideal ADC, code transitions are 1 LSB apart. DNL is the maximum deviation from this ideal value. It is often specified in terms of resolution for which no missing codes are guaranteed.
PAGE 13
AD7944 THEORY OF OPERATION IN+ MSB LSB 8192C 4096C 4C 2C C SWITCHES CONTROL SW+ C BUSY REF COMP REFGND 8192C 4096C 4C 2C C CONTROL LOGIC OUTPUT CODE C LSB MSB SW– 04658-005 CNV IN– Figure 21. ADC Simplified Schematic CIRCUIT INFORMATION The AD7944 is a fast, low power, single-supply, precise, 14-bit ADC using a successive approximation architecture. The AD7944 features different modes to optimize performance according to the application.
PAGE 14
AD7944 Transfer Functions Table 7. Output Codes and Ideal Input Voltages Description FSR − 1 LSB Midscale + 1 LSB Midscale Midscale − 1 LSB −FSR + 1 LSB −FSR 111 ... 111 111 ... 110 111 ... 101 1 2 000 ... 010 000 ... 000 –FSR Analog Input, VREF = 4.096 V 4.09575 V 2.04825 V 2.048 V 2.04775 V 250 µV 0V Digital Output Code (Hex) 0x3FFF1 0x2001 0x2000 0x1FFF 0x0001 0x00002 This is also the code for an overranged analog input (VIN+ − VIN− above VREF − REFGND).
PAGE 15
AD7944 ANALOG INPUTS DRIVER AMPLIFIER CHOICE Figure 24 shows an equivalent circuit of the analog input structure of the AD7944. Although the AD7944 is easy to drive, the driver amplifier must meet the following requirements: The two diodes, D1 and D2, provide ESD protection for the analog inputs, IN+ and IN−. Care must be taken to ensure that the analog input signal does not exceed the reference input voltage (VREF) by more than 0.3 V.
PAGE 16
AD7944 VOLTAGE REFERENCE INPUT Reference Decoupling The AD7944 allows the choice of a very low temperature drift internal voltage reference, an external reference, or an external buffered reference. The AD7944 voltage reference input, REF, has a dynamic input impedance that requires careful decoupling between the REF and REFGND pins. The Layout section describes how this can be done. To use the internal reference, the PDREF input must be low.
PAGE 17
AD7944 DIGITAL INTERFACE Although the AD7944 has a reduced number of pins, it offers flexibility in its serial interface modes. In CS mode, the AD7944 is compatible with SPI, MICROWIRE™, QSPI™, and digital hosts. In CS mode, the AD7944 can use either a 3-wire or a 4-wire interface. A 3-wire interface that uses the CNV, SCK, and SDO signals minimizes wiring connections, which is useful, for example, in isolated applications.
PAGE 18
AD7944 DATA READING OPTIONS There are three different data reading options for the AD7944. There is the option to read during conversion, to split the read across acquisition and conversion (see Figure 28 and Figure 29), and, in normal mode, to read during acquisition. The desired SCK frequency largely determines the reading option to use. To determine how to split the read for a particular SCK frequency, follow these examples to read data from conversion (n − 1). For turbo mode (2.
PAGE 19
AD7944 CS MODE, 3-WIRE WITHOUT BUSY INDICATOR minimum conversion time elapses and then held high for the maximum possible conversion time to avoid the generation of the busy signal indicator. This mode is usually used when a single AD7944 is connected to an SPI-compatible digital host. The connection diagram is shown in Figure 26, and the corresponding timing is given in Figure 27.
PAGE 20
AD7944 CS MODE, 3-WIRE WITH BUSY INDICATOR When the conversion is complete, SDO goes from high impedance to low impedance. With a pull-up on the SDO line, this transition can be used as an interrupt signal to initiate the data readback controlled by the digital host. The AD7944 then enters the acquisition phase and powers down. The data bits are then clocked out, MSB first, by subsequent SCK falling edges. The data is valid on both SCK edges.
PAGE 21
AD7944 CS MODE, 4-WIRE WITHOUT BUSY INDICATOR conversion time elapses and then held high for the maximum possible conversion time to avoid the generation of the busy signal indicator. This mode is usually used when multiple AD7944 devices are connected to an SPI-compatible digital host. A connection diagram example using two AD7944 devices is shown in Figure 30, and the corresponding timing is given in Figure 31.
PAGE 22
AD7944 CS MODE, 4-WIRE WITH BUSY INDICATOR used to select other SPI devices, such as analog multiplexers, but SDI must be returned low before the minimum conversion time elapses and then held low for the maximum possible conversion time to guarantee the generation of the busy signal indicator.
PAGE 23
AD7944 CHAIN MODE WITHOUT BUSY INDICATOR When the conversion is complete, the MSB is output onto SDO, and the AD7944 enters the acquisition phase and powers down. The remaining data bits stored in the internal shift register are clocked by subsequent SCK falling edges. For each ADC, SDI feeds the input of the internal shift register and is clocked by the SCK falling edge. Each ADC in the chain outputs its data MSB first, and 14 × N clocks are required to read back the N ADCs.
PAGE 24
AD7944 CHAIN MODE WITH BUSY INDICATOR When all ADCs in the chain have completed their conversions, the SDO pin of the ADC closest to the digital host (see the AD7944 ADC labeled C in Figure 36) is driven high. This transition on SDO can be used as a busy indicator to trigger the data readback controlled by the digital host. The AD7944 then enters the acquisition phase and powers down. The data bits stored in the internal shift register are clocked out, MSB first, by subsequent SCK falling edges.
PAGE 25
AD7944 APPLICATIONS INFORMATION LAYOUT The printed circuit board (PCB) that houses the AD7944 should be designed so that the analog and digital sections are separated and confined to certain areas of the board. The pinout of the AD7944, with its analog signals on the left side and its digital signals on the right side, eases this task. Avoid running digital lines under the device because they couple noise onto the die, unless a ground plane under the AD7944 is used as a shield.
PAGE 26
AD7944 AVDD BVDD REF REF REF PADDLE 1 2 GND GND GND GND 3 4 DVDD 5 6 GND 04658-030 GND VIO Figure 38. Example Layout of the AD7944 (Top Layer) 5V EXTERNAL REFERENCE (ADR435 OR ADR445) REF REF AVDD CAVDD CBVDD BVDD REF GND CREF GND GND GND GND CDVDD DVDD GND GND GND VIO CVIO 04658-031 GND Figure 39. Example Layout of the AD7944 (Bottom Layer) Rev.
PAGE 27
AD7944 OUTLINE DIMENSIONS 0.60 MAX 4.00 BSC SQ 0.60 MAX 15 PIN 1 INDICATOR 20 16 1 PIN 1 INDICATOR 3.75 BSC SQ 0.50 BSC 2.65 2.50 SQ 2.35 EXPOSED PAD (BOTTOM VIEW) 5 10 1.00 0.85 0.80 12° MAX 0.80 MAX 0.65 TYP 0.30 0.23 0.18 SEATING PLANE 0.50 0.40 0.30 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF 0.25 MIN FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET.