Datasheet

ManualsBrandsANALOG DEVICES ManualsData collecting ICsData acquisition IC - AD converter (ADC) External TSSOP 16

AD7993/AD7994

Rev. 0 | Page 21 of 32

Hysteresis Register (CH1/CH2/CH3/CH4)

Each hysteresis register is a 16-bit read/write register, of which

only the 12 LSBs of the register are used. The hysteresis register

stores the hysteresis value, N, when using the limit registers.

Each pair of limit registers has a dedicated hysteresis register.

The hysteresis value determines the reset point for the ALERT

pin/Alert_Flag if a violation of the limits has occurred. For

example, if a hysteresis value of 8 LSB is required on the upper

and lower limits of Channel 1, the 12-bit word, 0000 0000 0000

1000, should be written to the hysteresis register of CH1, the

address of which is shown in Table 8. On power-up, the

hysteresis registers contain a value of 8 LSB for the AD7994 and

2 LSB for the AD7993. If a different hysteresis value is required,

that value must be written to the hysteresis register for the

channel in question. For the AD7993, D1 and D0 of the

hysteresis register should contain 0s.

Table 20. Hysteresis Register (First Read/Write)

D15 D14 D13 D12 D11 D10 D9 D8

0 0 0 0 B11 B10 B9 B8

Table 21. Hysteresis Register (Second Read/Write)

D7 D6 D5 D4 D3 D2 D1 D0

B7 B6 B5 B4 B3 B2 B1 B0

Using the Limit Registers to Store Min/Max Conversion

Results for CH1 to CH4

If full scale, that is, all 1s, is written to the hysteresis register for

a particular channel, the DATA

HIGH

and DATA

LOW

registers for

that channel no longer act as limit registers as previously

described, but instead act as storage registers for the maximum

and minimum conversion results returned from conversions on

a channel over any given period of time. This function is useful

in applications where the widest span of actual conversion

results is required rather than using the alert to signal that an

intervention is necessary. This function could be useful for

monitoring temperature extremes during refrigerated goods

transportation.

It must be noted that on power-up, the contents of the

DATA

HIGH

contents of the DATA

LOW

registers are zero scale by default.

Therefore, minimum and maximum conversion values being

stored in this way are lost if power is removed or cycled.

ALERT STATUS REGISTER

The alert status register is an 8-bit read/write register that

provides information on an alert event. If a conversion results in

activating the ALERT pin or the Alert_Flag bit in the

conversion result register, as described in the Limit Registers

section, the alert status register may be read to gain further

information. It contains two status bits per channel, one

corresponding to the DATA

HIGH

limit and the other to the

DATA

LOW

limit. The bit with a status of 1 shows where the

violation occurred—that is, on which channel—and whether

the violation occurred on the upper or lower limit. If a second

alert event occurs on the other channel between receiving the

first alert and interrogating the alert status register, the

corresponding bit for that alert event is also set.

The entire contents of the alert status register may be cleared by

writing 1, 1 to Bits D2 and D1 in the configuration register, as

shown in Table 12. This may also be achieved by writing all 1s

to the alert status register itself. Therefore, if the alert status

contents of the alert status register are cleared or reset to all 0s.

Table 22. Alert Status Register

D7 D6 D5 D4 D3 D2 D1 D0

CH4

CH3

CH2

CH1

Table 23. Alert Status Register Bit Function Descriptions

Bit Mnemonic Comment

D0 CH1

Violation of DATA

LOW

limit on Channel 1 if

this bit set to 1, no violation if bit is set to 0.

D1 CH1

Violation of DATA

HIGH

limit on Channel 1 if