Datasheet
AD7993/AD7994
Rev. 0 | Page 4 of 32
Parameter B Version Unit Test Conditions/Comments
LOGIC INPUTS (CONVST)
Input High Voltage, V
INH
2.4 V min V
DD
= 5 V
2.0 V min V
DD
= 3 V
Input Low Voltage, V
INL
0.8 V max V
DD
= 5 V
0.4 V max V
DD
= 3 V
Input Leakage Current, I
IN
±1 µA max V
IN
= 0 V or V
DD
Input Capacitance, C
IN
3
10 pF max
LOGIC OUTPUTS (OPEN-DRAIN)
Output Low Voltage, V
OL
0.4 V max I
SINK
= 3 mA
0.6 V max I
SINK
= 6 mA
Floating-State Leakage Current ± 1 µA max
Floating-State Output Capacitance
3
10 pF max
Output Coding Straight (Natural) Binary
CONVERSION RATE See Modes of Operation section
Conversion Time 2 µs typ
Throughput Rate
Mode 1 (Reading after the Conversion) 5 kSPS typ f
SCL
= 100 kHz
21 kSPS typ f
SCL
= 400 kHz
121 kSPS typ f
SCL
= 3.4 MHz
Mode 2 5.5 kSPS typ f
SCL
= 100 kHz
22 kSPS typ f
SCL
= 400 kHz
147 kSPS typ f
SCL
= 3.4 MHz, 188 kSPS typ @ 5 V
POWER REQUIREMENTS
V
DD
2.7/5.5 V min/max
I
DD
Digital inputs = 0 V or V
DD
Power-Down Mode, Interface Inactive 1/2 µA max V
DD
= 3.3 V/5.5 V
Power-Down Mode, Interface Active 0.07/0.3 mA max V
DD
= 3.3 V/5.5 V, 400 kHz f
SCL
0.3/0.6 mA max V
DD
= 3.3 V/5.5 V, 3.4 MHz f
SCL
Operating, Interface Inactive 0.06/0.1 mA max V
DD
= 3.3 V/5.5 V, 400 kHz f
SCL
0.3/0.6 mA max V
DD
= 3.3 V/5.5 V, 3.4 MHz f
SCL
Operating, Interface Active 0.15/0.4 mA max V
DD
= 3.3 V/5.5 V, 400 kHz f
SCL
0.6/1.1 mA max V
DD
= 3.3 V/5.5 V, 3.4 MHz f
SCL
Mode 1
0.7/1.4 mA typ V
DD
= 3.3 V/5.5 V, 3.4 MHz f
SCL
Mode 2
Mode 3 (I
2
C Inactive, T
CONVERT
x 32) 0.7/1.5 mA max V
DD
= 3.3 V/5.5 V
POWER DISSIPATION
Fully Operational
Operating, Interface Active 0.495/2.2 mW max V
DD
= 3.3 V/5.5 V, 400 kHz f
SCL
1.98/6.05 mW max V
DD
= 3.3 V/5.5 V, 3.4 MHz f
SCL
Mode 1
2.31/7.7 mW typ V
DD
= 3.3 V/5.5 V, 3.4 MHz f
SCL
Mode 2
Power-Down, Interface Inactive 3.3/11 µW max V
DD
= 3.3 V/5.5 V
1
Min/max ac dynamic performance, INL and DNL specifications are typical specifications when operating in Mode 2 with I
2
C high speed mode SCL frequencies.
Specifications outlined for Mode 2 apply to Mode 3 also. Sample delay and bit trial delay enabled.
2
See the Terminology section.
3
Guaranteed by initial characterization.