Datasheet

ManualsBrandsANALOG DEVICES ManualsLinear ICsAD80066KRSZ

Complete 16-Bit

CCD/CIS Signal Processor

AD80066

Rev. A

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FEATURES

16-bit, 24 MSPS analog-to-digital converter (ADC)

4-channel operation up to 24 MHz (6 MHz/channel)

3-channel operation up to 24 MHz (8 MHz/channel)

Selectable input range: 3 V or 1.5 V peak-to-peak

Input clamp circuitry

Correlated double sampling

1×~6× programmable gain

±300 mV programmable offset

Internal voltage reference

Multiplexed byte-wide output

Optional single-byte output mode

3-wire serial digital interface

3 V/5 V digital I/O compatibility

Power dissipation: 490 mW at 24 MHz operation

Reduced power mode and sleep mode available

28-lead SSOP package

APPLICATIONS

Flatbed document scanners

Film scanners

Digital color copiers

Multifunction peripherals

GENERAL DESCRIPTION

The AD80066 is a complete analog signal processor for imaging

applications. It features a 4-channel architecture designed to sample

and condition the outputs of linear charged coupled device (CCD)

or contact image sensor (CIS) arrays. Each channel consists of

an input clamp, correlated double sampler (CDS), offset digital-

to-analog converter (DAC), and programmable gain amplifier

(PGA), multiplexed to a high performance 16-bit ADC. For

maximum flexibility, the AD80066 can be configured as a

4-channel, 3-channel, 2-channel, or 1-channel device.

The CDS amplifiers can be disabled for use with sensors that

do not require CDS, such as CIS and CMOS sensors.

The 16-bit digital output is multiplexed into an 8-bit output word,

which is accessed using two read cycles. There is an optional

single-byte output mode. The internal registers are programmed

through a 3-wire serial interface and enable adjustment of the

gain, offset, and operating mode. The AD80066 operates from a

5 V power supply, typically consumes 490 mW of power, and is

packaged in a 28-lead SSOP.

FUNCTIONAL BLOCK DIAGRAM

DOUT

(D[0:7])

SCLK

SLOAD

SDATA

ADCCLK

OFFSET

AVDD AVSS CML

VDD CAPT CAPB

AD80066

DRVDD DRVSS

GAIN

REGISTERS

OFFSET

REGISTERS

4:1

MUX

16-BIT

ADC

CH. A

CH. B

CH. C

CH. D

CH. A

CH. B

CH. C

CH. D

PGA

CDS

VSS

VIND

VINC

VINB

VINA

CDS

DIGITAL

CONTROL

INTERFACE

INPUT

CLAMP

BIAS

9-BIT

DAC

9-BIT

DAC

9-BIT

DAC

9-BIT

DAC

PGA

CONFIGURATION

MUX

CDSCLK2CDSCLK1

BAND GAP

REFERENCE

16:8

MUX

8552-001

Figure 1.

Summary of content (21 pages)

PAGE 1
Complete 16-Bit CCD/CIS Signal Processor AD80066 FEATURES GENERAL DESCRIPTION 16-bit, 24 MSPS analog-to-digital converter (ADC) 4-channel operation up to 24 MHz (6 MHz/channel) 3-channel operation up to 24 MHz (8 MHz/channel) Selectable input range: 3 V or 1.
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AD80066 TABLE OF CONTENTS Features .............................................................................................. 1 1-Channel CDS Mode ............................................................... 13 Applications ....................................................................................... 1 1-Channel SHA Mode ............................................................... 13 General Description .........................................................................
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AD80066 SPECIFICATIONS ANALOG SPECIFICATIONS TMIN to TMAX, AVDD = 5 V, DRVDD = 5 V, CDS mode, fADCCLK = 24 MHz, fCDSCLK1 = fCDSCLK2 = 6 MHz, PGA gain = 1, unless otherwise noted. Table 1.
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AD80066 Parameter POWER DISSIPATION 4-Channel Mode at 24 MHz 1-Channel Mode at 12 MHz 4-Channel Mode at 8 MHz, Slow Power Mode 3 1 2 3 Min Typ Max Unit 490 300 165 mW mW mW The linear input signal range is up to 3 V p-p when the CCD reference level is clamped to 3 V by the AD80066 input clamp (see Figure 2). The PGA gain is approximately linear-in-dB but varies nonlinearly with register code (see the Programmable Gain Amplifiers (PGA) section for more information).
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AD80066 TIMING SPECIFICATIONS TMIN to TMAX, AVDD = 5 V, DRVDD = 5 V. Table 3.
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AD80066 PIXEL n (A, B, C) ANALOG INPUTS PIXEL (n + 1) PIXEL (n + 2) tAD tAD tC2C1 tC1 tPRA CDSCLK1 tC1C2 tC2 tC2ADF CDSCLK2 tADC2 tADCCLK tC2ADR ADCCLK OUTPUT DATA (D[7:0]) A(n – 2) B(n – 2) B(n – 2) C(n – 2) C(n – 2) A(n – 1) A(n – 1) B(n – 1) B(n – 1) C(n – 1) C(n – 1) HIGH BYTE LOW BYTE HIGH BYTE LOW BYTE HIGH BYTE LOW BYTE HIGH BYTE LOW BYTE HIGH BYTE LOW BYTE A(n) A(n) B(n) B(n) HIGH BYTE LOW BYTE HIGH BYTE LOW BYTE 08552-004 tOD tADCCLK Figure 4.
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AD80066 PIXEL n ANALOG INPUTS PIXEL (n + 1) PIXEL (n + 2) tAD tAD tC1 tC2C1 tPRB CDSCLK1 tC1C2 tC2 CDSCLK2 tC2ADR tC2ADF ADCCLK tADCCLK tADCCLK PIXEL (n – 4) PIXEL (n – 4) PIXEL (n – 3) PIXEL (n – 3) PIXEL (n – 2) PIXEL (n – 2) LOW BYTE HIGH BYTE LOW BYTE HIGH BYTE LOW BYTE HIGH BYTE 08552-006 OUTPUT DATA (D[7:0]) tOD NOTES 1. IN 1-CHANNEL CDS MODE. THE CDSCLK1 FALLING EDGE AND THE CDSCLK2 RISING EDGE MUST OCCUR WHILE ADCCLK IS LOW. Figure 6.
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AD80066 PIXEL n PIXEL (n + 1) tAD ANALOG INPUTS tPRB tC2 CDSCLK2 tC2ADR tC2ADF tADCCLK ADCCLK tADCCLK PIXEL (n – 4) PIXEL (n – 4) PIXEL (n – 3) PIXEL (n – 3) PIXEL (n – 2) PIXEL (n – 2) HIGH BYTE LOW BYTE HIGH BYTE LOW BYTE HIGH BYTE LOW BYTE 08552-008 OUTPUT DATA (D[7:0]) tOD Figure 8.
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AD80066 ABSOLUTE MAXIMUM RATINGS Table 4. Parameter VINx, CAPT, CAPB Digital Inputs SDATA AVDD DRVDD AVSS Digital Outputs (D[7:0]) Temperature Junction Storage Lead (10 sec) With Respect To AVSS AVSS DRVSS AVSS DRVSS DRVSS DRVSS Rating −0.3 V to AVDD + 0.3 V −0.3 V to AVDD + 0.3 V −0.3 V to DRVDD −0.5 V to +6.5 V −0.5 V to +6.5 V −0.3 V to +0.3 V −0.3 V to DRVDD + 0.
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AD80066 28 AVSS CDSCLK1 AVDD 1 2 27 VINA CDSCLK2 3 26 OFFSET ADCCLK 4 25 VINB DRVDD 5 24 CML DRVSS 6 23 VINC 22 CAPT 21 CAPB 20 VIND D4 10 19 AVSS D3 11 18 AVDD D2 12 17 SLOAD D1 13 16 SCLK (LSB) D0 14 15 SDATA AD80066 (MSB) D7 7 TOP VIEW (Not to Scale) D6 8 D5 9 08552-013 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Figure 13. Pin Configuration Table 6. Pin Function Descriptions Pin No.
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AD80066 1.0 15 0.5 10 INL (LSB) 0 –0.5 0 0 12,800 25,600 38,400 51,200 64,000 ADC OUTPUT CODE 08552-014 –1.0 50 45 40 35 30 25 20 15 10 0 15 30 45 PGA REGISTER VALUE (Decimal) 63 08552-015 5 0 –5 0 12,800 25,600 38,400 51,200 ADC OUTPUT CODE Figure 16. Typical INL Performance Figure 14. Typical DNL Performance OUTPUT NOISE (LSB) 5 Figure 15. Output Noise vs. PGA Gain Rev.
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AD80066 TERMINOLOGY Integral Nonlinearity (INL) Integral nonlinearity error refers to the deviation of each individual code from a line drawn from zero scale through positive full scale. The point used as zero scale occurs ½ LSB before the first code transition. Positive full scale is defined as a level 1½ LSB beyond the last code transition. The deviation is measured from the middle of each particular code to the true straight line.
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AD80066 THEORY OF OPERATION The AD80066 can be operated in several different modes, including 4-channel CDS mode, 4-channel SHA mode, 1-channel CDS mode, and 1-channel SHA mode. Each mode is selected by programming the configuration register through the serial interface. For more information on CDS or SHA mode operation, see the Circuit Operation section. 4-CHANNEL CDS MODE In 4-channel CDS mode, the AD80066 simultaneously samples the A, B, C, and D input voltages from the CCD outputs.
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AD80066 INTERNAL REGISTER MAP Table 7. Internal Register Map Register Name Configuration Mux Gain A Gain B Gain C Gain D Offset A Offset B Offset C Offset D A3 0 0 0 0 0 0 0 0 1 1 Address A2 A1 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 0 0 0 0 A0 0 1 0 1 0 1 0 1 0 1 D8 0 0 0 0 0 0 MSB MSB MSB MSB D7 0 0 0 0 0 0 D6 0 0 0 0 0 0 D5 VREF 0 MSB MSB MSB MSB D4 2/1 byte Ch. order Rev. A | Page 14 of 20 Data Bits D3 CDS on Ch. A D2 Input range Ch. B D1 Fast/slow Ch. C D0 Power on Ch.
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AD80066 INTERNAL REGISTER DETAILS the CDSCLK2 pulse always resets the multiplexer to sample the A channel first. When Bit D4 is set high, the channel order is reversed to D, C, B, and A. The CDSCLK2 pulse always resets the multiplexer to sample the D channel first. Bits D[3:0] are used when operating in 1-channel mode. Bit D3 is set high to sample the A channel. Bit D2 is set high to sample the B channel. Bit D1 is set high to sample the C channel. Bit D0 is set high to sample the D channel.
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AD80066 Table 11. Offset Register Settings (MSB) D8 0 0 … 0 1 1 … 1 1 D7 0 0 … 1 0 0 … 1 D6 0 0 … 1 0 0 … 1 D5 0 0 … 1 0 0 … 1 D4 0 0 … 1 0 0 … 1 D3 0 0 … 1 0 0 … 1 D2 0 0 … 1 0 0 … 1 Power-on default value. Rev. A | Page 16 of 20 D1 0 0 … 1 0 0 … 1 (LSB) D0 01 1 … 1 0 1 … 1 Offset (mV) 0 +1.2 … +300 0 −1.
PAGE 18
AD80066 CIRCUIT OPERATION ANALOG INPUTS—CDS MODE EXTERNAL INPUT COUPLING CAPACITORS Figure 17 shows the analog input configuration for the CDS mode of operation. Figure 18 shows the internal timing for the sampling switches. The CCD reference level is sampled when CDSCLK1 transitions from high to low, opening S1. The CCD data level is sampled when CDSCLK2 transitions from high to low, opening S2.
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AD80066 ANALOG INPUTS—SHA MODE AD80066 Figure 19 shows the analog input configuration for the SHA mode of operation. Figure 20 shows the internal timing for the sampling switches. The input signal is sampled when CDSCLK2 transitions from high to low, opening S1. The voltage on the OFFSET pin is also sampled on the falling edge of CDSCLK2, when S2 opens. S3 is then closed, generating a differential output voltage that represents the difference between the sampled input voltage and the OFFSET voltage.
PAGE 20
AD80066 APPLICATIONS INFORMATION CDSCLK2 should occur coincident with or before the rising edge of ADCCLK (see Figure 3 through Figure 8 for timing). All 0.1 μF decoupling capacitors should be located as close as possible to the AD80066 pins. When operating in 1-channel mode, the unused analog inputs should be grounded. CIRCUIT AND LAYOUT RECOMMENDATIONS Figure 23 shows the recommended circuit configuration for 4-channel CDS mode operation. The recommended input coupling capacitor value is 0.
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AD80066 OUTLINE DIMENSIONS 10.50 10.20 9.90 15 28 5.60 5.30 5.00 1 8.20 7.80 7.40 14 0.65 BSC 0.38 0.22 SEATING PLANE 8° 4° 0° COMPLIANT TO JEDEC STANDARDS MO-150-AH 0.95 0.75 0.55 060106-A 0.05 MIN COPLANARITY 0.10 0.25 0.09 1.85 1.75 1.65 2.00 MAX Figure 25.