Datasheet

Data Sheet AD8016
Rev. C | Page 15 of 20
The bias level can be controlled with TTL logic levels (high = 1)
applied to the PWDN1 and PWDN0 pins alone or in combina-
tion with the BIAS control pin. The DGND or digital ground
pin is the logic ground reference for the PWDN1 and PWDN0
pins. In typical ADSL applications where ±12 V or ±6 V
supplies (also single supplies) are used, the DGND pin is
connected to analog ground.
The BIAS control pin by itself is a means to continuously adjust
the AD8016 internal biasing and, thus, quiescent current I
Q
. By
pulling out a current of 0 μA (or open) to approximately200 μA,
the quiescent current can be adjusted from 100% (full on) to a
full off condition. The full off condition yields a high output
impedance. Because of an on-chip resistor variation of up to
±20%, the actual amount of current required to fully shut down
the AD8016 can vary. To institute a full chip shutdown, a pull-
down current of 250 μA is recommended. See Figure 43 for the
logic drive circuit for complete amplifier shutdown. Figure 37
and Figure 38 show the relationship between current pulled out
of the BIAS pin (I
BIAS
) and the supply current (I
Q
). A typical
shutdown I
Q
is less than 1 mA total. Alternatively, an external
pull-down resistor to ground or a current sink attached to the
BIAS pin can be used to set I
Q
to lower levels (see Figure 44).
The BIAS pin may be used in combination with the PWDN1
and PWDN0 pins; however, diminished MTPR performance
may result when I
Q
is lowered too much. Current pulled away
from the BIAS pin shunts away a portion of the internal bias
current. Setting PWDN1 or PWDN0 to Logic 0 also shunts
away a portion of the internal bias current. The reduction of
quiescent bias levels due to the use of PWDN1 and PWDN0 is
consistent with the percentages established in Table 7. When
PWDN0 alone is set to Logic 0, and no other means of reducing
the internal bias currents is used, full-rate ADSL signals may be
driven while maintaining reasonable levels of MTPR.
Figure 43. Logic Drive of BIAS Pin for Complete Amplifier Shutdown
THERMAL SHUTDOWN
The AD8016 ARB is designed to incorporate shutdown
protection against accidental thermal overload. In the event
of thermal overload, the AD8016 was designed to shut down
at a junction temperature of 165°C and return to normal
operation at a junction temperature 140°C. The AD8016
continues to operate, cycling on and off, as long as the thermal
overload condition remains. The frequency of the protection
cycle depends on the ambient environment, severity of the
thermal overload condition, the power being dissipated, and
the thermal mass of the PCB beneath the AD8016. When the
AD8016 begins to cycle due to thermal stress, the internal
shutdown circuitry draws current out of the node connected
in common with the BIAS pin, while the voltage at the BIAS
pin goes to the negative rail. When the junction temperature
returns to 140°C, current is no longer drawn from this node,
and the BIAS pin voltage returns to the positive rail. Under
these circumstances, the BIAS pin can be used to trip an alarm
indicating the presence of a thermal overload condition.
Figure 44 also shows three circuits for converting this signal to
a standard logic level.
Figure 44. Shutdown and Alarm Circuit
R2
50kΩ
BIAS
R1*
3.3V LOGIC
2N3904
*
R1 = 47kΩ FOR ±12V
S
OR +12V
S
,
R1 = 22kΩ FOR ±6
V
S
.
01019-043
5V
BIAS
ALARM
1/4 HCF 40109B
SGS–THOMSON
5V
1MΩ
BIAS
ALARM
MIN β 350
OR
V
EE
10kΩ
10kΩ
10kΩ
100kΩ
200µA
0µA – 200µA
V
CC
V
CC
BIAS
PWDN1
BIAS
OR
V = V
CC
–0.2V
SHUT-
DOWN
AD8016
PWDN0
01019-044