Datasheet

AD8108/AD8109
Rev. B | Page 6 of 32
TIMING CHARACTERISTICS (PARALLEL)
Table 4. Timing Characteristics
Parameter Symbol Min Typ Max Unit
Data Setup Time t
1
20 ns
CLK Pulse Width t
2
100 ns
Data Hold Time t
3
20 ns
CLK Pulse Separation t
4
100 ns
CLK to UPDATE Delay
t
5
0 ns
UPDATE Pulse Width
t
6
50 ns
Propagation Delay, UPDATE to Switch On or Off
– 8 ns
CLK, UPDATE Rise and Fall Times
– 100 ns
RESET Time
– 200 ns
Table 5. Logic Levels
V
IH
V
IL
V
OH
V
OL
I
IH
I
IL
I
OH
I
OL
RESET, SER/PAR
CLK, D0, D1, D2,
D3, A0, A1, A2
CE, UPDATE
RESET, SER/PAR
CLK, D0, D1, D2,
D3, A0, A1, A2
CE, UPDATE
DATA OUT DATA OUT
RESET, SER/PAR
CLK, D0, D1, D2,
D3, A0, A1, A2
CE, UPDATE
RESET SER/PAR
CLK, D0, D1, D2,
D3, A0, A1, A2
CE, UPDATE
DATA OUT DATA OUT
2.0 V min 0.8 V max 2.7 V min 0.5 V max 20 µA max −400 µA min −400 µA max 3.0 mA min
1
0
1
0
D0–D3
A0–A2
CLK
1 = LATCHED
UPDATE
0 = TRANSPAREN
T
t
2
t
1
t
5
t
6
t
3
t
4
01068-003
Figure 3. Timing Diagram, Parallel Mode