Datasheet

ManualsBrandsANALOG DEVICES ManualsInterface ICsInterface IC - analogue switches LQFP 80

AD8108/AD8109

Rev. B | Page 7 of 32

Table 6. Operation Truth Table

UPDATE

CLK DATA IN DATA OUT

RESET

SER

PAR

Operation/Comment

1 X X X X X X No change in logic.

0 1

Data

i-32

1 0

The data on the serial DATA IN line is loaded into serial register. The

first bit clocked into the serial register appears at DATA OUT 32 clocks

later.

0 1

D0 … D3,

A0 … A2

NA in parallel

mode

1 1

The data on the parallel data lines, D0 to D3, are loaded into the

32-bit serial shift register location addressed by A0 to A2.

0 0 X X… X 1 X

Data in the 32-bit shift register transfers into the parallel latches that

control the switch array. Latches are transparent.

X X X X X 0 X

Asynchronous operation. All outputs are disabled. Remainder of logic

is unchanged.

CLK

3 TO 8 DECODER

CLK

RESET

OUT0

QCLR

DATA IN

(SERIAL)

(OUTPUT ENABLE)

SER/PAR

OUT0 EN

DATA

OUT

PARALLEL DAT

CLK

OUT1 EN

OUT2 EN

OUT3 EN

OUT4 EN

OUT5 EN

OUT6 EN

OUT7 EN

OUT0

OUT1

OUT6

QCLR

OUT7

QCLR

DECODE

OUTPUT ENABLESWITCH MATRIX

01068-011

Figure 4. Logic Diagram