Datasheet

REV. A
AD8113
–6–
Table III. Operation Truth Table
SER/
CE UPDATE CLK DATA IN DATA OUT RESET PAR Operation/Comment
1X XX XXXNo change in logic.
01 f Data
i
Data
i-80
10The data on the serial DATA IN line is loaded
into serial register. The first bit clocked into
the serial register appears at DATA OUT 80
clocks later.
01 f D0 . ..D4, NA in Parallel 1 1 The data on the parallel data lines, D0–D4, are
A0 ...A3 Mode loaded into the 80-bit serial shift register loca-
tion addressed by A0–A3.
00 XX X1XData in the 80-bit shift register transfers into the
parallel latches that control the switch array.
Latches are transparent.
XX XX X0XAsynchronous operation. All outputs are disabled.
Remainder of logic is unchanged.
D
CLK
Q
4 TO 16 DECODER
A0
A1
A2
CLK
CE
UPDATE
16
256
DATA IN
(SERIAL)
(OUTPUT
ENABLE)
SER/PAR
RESET
(OUTPUT ENABLE)
OUT0 EN
DATA
OUT
PARALLEL
DATA
DQ
CLK
DQ
CLK
DQ
CLK
DQ
CLK
D1
D2
D3
DQ
CLK
DQ
CLK
DQ
CLK
DQ
CLK
D
Q
CLK
OUT1 EN
OUT2 EN
OUT3 EN
OUT4 EN
OUT5 EN
OUT6 EN
OUT7 EN
DLE
QCLR
OUT15
EN
OUTPUT ENABLESWITCH MATRIX
S
D1
Q
D0
D0
S
D1
Q
D0
S
D1
Q
D0
S
D1
Q
D0
S
D1
Q
D0
S
D1
Q
D0
S
D1
Q
D0
S
D1
Q
D0
DQ
CLK
S
D1
Q
D0
D4
DECODE
DLE
QCLR
OUT0
EN
DLE
OUT0
B0
Q
DLE
Q
OUT0
B1
DLE
Q
OUT0
B2
DLE
Q
OUT0
B3
DLE
OUT1
B0
Q
DLE
QCLR
OUT14
EN
DLE
OUT15
B0
Q
DLE
OUT15
B1
Q
DLE
OUT15
B2
Q
DQ
CLK
S
D1
Q
D0
S
D1
Q
D0
DLE
OUT15
B3
Q
S
D1
Q
D0
OUT8 EN
OUT9 EN
OUT10 EN
OUT11 EN
OUT12 EN
OUT13 EN
OUT14 EN
OUT15 EN
A3
OUTPUT
ADDRESS
Figure 4. Logic Diagram