Datasheet

AD8120 Data Sheet
Rev. A | Page 12 of 16
I
2
C Control
The I
2
C interface of the AD8120 is a 2-wire interface consisting
of a clock input and a bidirectional data line. The AD8120
drives the SDA line either to acknowledge the master (ACK) or
to send data during a read operation. The SDA pin for the I
2
C
port is open drain and requires a 10 kΩ pull-up resistor.
Table 9. AD8120 I
2
C Pin Descriptions
Pin No. Pin Name Description
2 SDA Serial data input/output
30 SCL Serial clock input
29 A1 I
2
C Address Bit A1
31
A0
I
2
C Address Bit A0
The AD8120 address consists of a built-in address of 0x38 and the
two address pins, A0 and A1. The two address pins enable up to
four AD8120 devices to be used in a system (see Table 10). Both
address pins must be terminated (high or low) for the AD8120
I
2
C interface to operate properly.
Table 10. I
2
C Addresses
A1 Pin A0 Pin I
2
C Address
0 0 0x38
0 1 0x39
1 0 0x3A
1 1 0x3B
In I
2
C mode, the AD8120 is programmed with a 3-byte sequence
for a write operation (see Figure 19) and a 4-byte sequence for a
read operation (see Figure 20). The first byte contains the 7-bit
device address and the R/
W
instruction bit. The second byte con-
tains the color register.
In write mode, the third byte contains the delay code. In read
mode, the third byte contains the device address, and the fourth
byte contains the stored delay code.
START BY
MASTER
STOP BY
MASTER
ACK BY
AD8120
ACK BY
AD8120
ACK BY
AD8120
0
1
1 99
1 1 1 0 A1 A0 00
0 0 0 0 0 C1 C0
SCL
SDA
SDA (CONTINUED)
SCL (CONTINUED)
91
X X D5 D4 D3
D2
D1
D0
R/W
07839-023
BYTE 1
I
2
C ADDRESS
BYTE 2
COLOR REGISTER
BYTE 3
DELAY DATA CODE
Figure 19. I
2
C Write Sequence
START BY
MASTER
ACK BY
AD8120
ACK BY
AD8120
R/W
SCL
1 1 99
SDA
0 1 1 1 0
0 1 1 1 0
A1 A0 00 0 0 0 0 0 C1 C0
BYTE 1
I
2
C ADDRESS
BYTE 2
COLOR REGISTER
BYTE 3
I
2
C ADDRESS
BYTE 4
DATA BYTE FROM AD8120
STOP BY
MASTER
START BY
MASTER
ACK BY
AD8120
NO ACK BY
AD8120
SCL
1 1 99
SDA
A1 A0 1 X X D5 D4 D3 D2 D1 D0
R/W
07839-024
Figure 20. I
2
C Read Sequence